Issued Patents 2002
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6468877 | Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner | Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Ravi Sundaresan, Yang Pan +2 more | 2002-10-22 |
| 6468851 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Mei Sheng Zhou +1 more | 2002-10-22 |
| 6461900 | Method to form a self-aligned CMOS inverter using vertical device integration | Ravi Sundaresan, Yang Pan, James Lee Yong Meng, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more | 2002-10-08 |
| 6461887 | Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth | Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Ravi Sundaresan, Yang Pan +2 more | 2002-10-08 |
| 6455377 | Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) | Jia Zhen Zheng, Lap Chan, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2002-09-24 |
| 6440800 | Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2002-08-27 |
| 6436770 | Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation | Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Ravi Sundaresan +2 more | 2002-08-20 |
| 6436774 | Method for forming variable-K gate dielectric | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2002-08-20 |
| 6429109 | Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate | Jia Zhen Zheng, Mei Sheng Zhou, Daniel Yen, Chew Hoe Ang, Eng Hua Lim +1 more | 2002-08-06 |
| 6417056 | Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge | Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more | 2002-07-09 |
| 6417054 | Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide | Jia Zhen Zheng, Lap Chan, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2002-07-09 |
| 6406945 | Method for forming a transistor gate dielectric with high-K and low-K regions | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2002-06-18 |
| 6403485 | Method to form a low parasitic capacitance pseudo-SOI CMOS device | Ravi Sundaresan, Yang Pan, James Lee Yong Meng, Ying Keung, Yelehanka Ramachandramurthy Pradeep +2 more | 2002-06-11 |
| 6380610 | Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect | Igor Peidous, Konstantin V. Loiko, David Yeo Yong Hock | 2002-04-30 |
| 6380088 | Method to form a recessed source drain on a trench side wall with a replacement gate technique | Lap Chan, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2002-04-30 |