YP

Yang Pan

CM Chartered Semiconductor Manufacturing: 16 patents #6 of 191Top 4%
📍 Los Altos, CA: #2 of 415 inventorsTop 1%
🗺 California: #63 of 26,763 inventorsTop 1%
Overall (2002): #437 of 266,432Top 1%
16
Patents 2002

Issued Patents 2002

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
6498386 Cylindrical semiconductor capacitor 2002-12-24
6468877 Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan +2 more 2002-10-22
6461900 Method to form a self-aligned CMOS inverter using vertical device integration Ravi Sundaresan, James Lee Yong Meng, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng +2 more 2002-10-08
6461887 Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan +2 more 2002-10-08
6455377 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, James Yong Meng Lee +2 more 2002-09-24
6451706 Attenuation of reflecting lights by surface treatment Ron Fu Chu, Qun Ying Lin, Mei Sheng Zhou 2002-09-17
6440800 Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more 2002-08-27
6436774 Method for forming variable-K gate dielectric James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more 2002-08-20
6436770 Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek +2 more 2002-08-20
6417054 Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, James Yong Meng Lee +2 more 2002-07-09
6417056 Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge Elgin Quek, Ravi Sundaresan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more 2002-07-09
6406945 Method for forming a transistor gate dielectric with high-K and low-K regions James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more 2002-06-18
6403485 Method to form a low parasitic capacitance pseudo-SOI CMOS device Elgin Quek, Ravi Sundaresan, James Lee Yong Meng, Ying Keung, Yelehanka Ramachandramurthy Pradeep +2 more 2002-06-11
6380506 Use of hot carrier effects to trim analog transistor pair 2002-04-30
6380088 Method to form a recessed source drain on a trench side wall with a replacement gate technique Lap Chan, Elgin Quek, Ravi Sundaresan, James Yong Meng Lee, Ying-Keung Leung +2 more 2002-04-30
6354781 Semiconductor manufacturing system 2002-03-12