Issued Patents All Time
Showing 25 most recent of 140 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11893159 | Multi-component detection of gestures | Maurizio Paganini, Harshit Khaitan | 2024-02-06 |
| 11620220 | Cache system with a primary cache and an overflow cache that use different indexing schemes | Colin Eddy | 2023-04-04 |
| 11467675 | Multi-component detection of gestures | Maurizio Paganini, Harshit Khaitan | 2022-10-11 |
| 11061853 | Processor with memory controller including dynamically programmable functional unit | G. Glenn Henry, Terry Parks, Douglas R. Reed | 2021-07-13 |
| 10642617 | Processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Terry Parks, Douglas R. Reed | 2020-05-05 |
| 10514920 | Dynamically updating hardware prefetch trait to exclusive or shared at program detection | Albert J. Loper, John Michael Greer | 2019-12-24 |
| 10423216 | Asymmetric multi-core processor with native switching mechanism | Terry Parks, G. Glenn Henry | 2019-09-24 |
| 10387318 | Prefetching with level of aggressiveness based on effectiveness by memory access type | Douglas R. Reed, John Michael Greer, Colin Eddy | 2019-08-20 |
| 10268586 | Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests | G. Glenn Henry, Terry Parks, Douglas R. Reed | 2019-04-23 |
| 10268587 | Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests | G. Glenn Henry, Terry Parks, Douglas R. Reed | 2019-04-23 |
| 10235232 | Processor with approximate computing execution unit that includes an approximation control register having an approximation mode flag, an approximation amount, and an error threshold, where the approximation control register is writable by an instruction set instruction | G. Glenn Henry, Terry Parks | 2019-03-19 |
| 10146543 | Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Terry Parks, Douglas R. Reed | 2018-12-04 |
| 10127041 | Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Terry Parks, Douglas R. Reed | 2018-11-13 |
| 10073787 | Dynamic powering of cache memory by ways within multiple set groups based on utilization trends | Douglas R. Reed | 2018-09-11 |
| 10067871 | Logic analyzer for detecting hangs | Douglas R. Reed | 2018-09-04 |
| 10019260 | Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match | G. Glenn Henry, Colin Eddy, Terry Parks | 2018-07-10 |
| 9972375 | Sanitize-aware DRAM controller | Terry Parks, Douglas R. Reed | 2018-05-15 |
| 9952875 | Microprocessor with ALU integrated into store unit | Gerard M. Col, Colin Eddy | 2018-04-24 |
| 9946651 | Pattern detector for detecting hangs | Douglas R. Reed | 2018-04-17 |
| 9911508 | Cache memory diagnostic writeback | Stephan Gaskins, Douglas R. Reed, Jason Chen | 2018-03-06 |
| 9910785 | Cache memory budgeted by ways based on memory access type | Douglas R. Reed, John Michael Greer, Colin Eddy | 2018-03-06 |
| 9898411 | Cache memory budgeted by chunks based on memory access type | Douglas R. Reed, John Michael Greer, Colin Eddy | 2018-02-20 |
| 9898291 | Microprocessor with arm and X86 instruction length decoders | G. Glenn Henry, Terry Parks | 2018-02-20 |
| 9891916 | Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent system | Albert J. Loper, John Michael Greer, Meera Ramani-Augustin | 2018-02-13 |
| 9891927 | Inter-core communication via uncore RAM | G. Glenn Henry, Terry Parks, Stephan Gaskins | 2018-02-13 |