Issued Patents All Time
Showing 25 most recent of 277 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12380033 | Refreshing cache regions using a memory controller and multiple tables | Douglas R. Reed, Al Loper | 2025-08-05 |
| 11934310 | Zero bits in L3 tags | Douglas R. Reed, Al Loper | 2024-03-19 |
| 11226840 | Neural network unit that interrupts processing core upon condition | G. Glenn Henry | 2022-01-18 |
| 11221872 | Neural network unit that interrupts processing core upon condition | G. Glenn Henry | 2022-01-11 |
| 11061853 | Processor with memory controller including dynamically programmable functional unit | G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed | 2021-07-13 |
| 10776690 | Neural network unit with plurality of selectable output functions | G. Glenn Henry | 2020-09-15 |
| 10725934 | Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode | G. Glenn Henry, Douglas R. Reed | 2020-07-28 |
| 10671564 | Neural network unit that performs convolutions using collective shift register among array of neural processing units | G. Glenn Henry, Kyle T. O'Brien | 2020-06-02 |
| 10642617 | Processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed | 2020-05-05 |
| 10635453 | Dynamic reconfiguration of multi-core processor | G. Glenn Henry, Darius D. Gaskins | 2020-04-28 |
| 10585848 | Processor with hybrid coprocessor/execution unit neural network unit | G. Glenn Henry | 2020-03-10 |
| 10552370 | Neural network unit with output buffer feedback for performing recurrent neural network computations | G. Glenn Henry, Kyle T. O'Brien | 2020-02-04 |
| 10509765 | Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value | G. Glenn Henry | 2019-12-17 |
| 10474627 | Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory | G. Glenn Henry | 2019-11-12 |
| 10474628 | Processor with variable rate execution unit | G. Glenn Henry | 2019-11-12 |
| 10423216 | Asymmetric multi-core processor with native switching mechanism | Rodney E. Hooker, G. Glenn Henry | 2019-09-24 |
| 10409767 | Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory | G. Glenn Henry | 2019-09-10 |
| 10394562 | Microprocessor that fuses if-then instructions | G. Glenn Henry | 2019-08-27 |
| 10387366 | Neural network unit with shared activation function units | G. Glenn Henry | 2019-08-20 |
| 10380064 | Neural network unit employing user-supplied reciprocal for normalizing an accumulated value | G. Glenn Henry | 2019-08-13 |
| 10380481 | Neural network unit that performs concurrent LSTM cell calculations | G. Glenn Henry, Kyle T. O'Brien | 2019-08-13 |
| 10366050 | Multi-operation neural network unit | G. Glenn Henry | 2019-07-30 |
| 10353862 | Neural network unit that performs stochastic rounding | G. Glenn Henry | 2019-07-16 |
| 10353861 | Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource | G. Glenn Henry | 2019-07-16 |
| 10353860 | Neural network unit with neural processing units dynamically configurable to process multiple data sizes | G. Glenn Henry | 2019-07-16 |