Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12380033 | Refreshing cache regions using a memory controller and multiple tables | Al Loper, Terry Parks | 2025-08-05 |
| 12099444 | Cat aware loads and software prefetches | — | 2024-09-24 |
| 12013784 | Prefetch state cache (PSC) | Akarsh Dolthatta Hebbar | 2024-06-18 |
| 11940921 | Bounding box prefetcher | — | 2024-03-26 |
| 11934310 | Zero bits in L3 tags | Al Loper, Terry Parks | 2024-03-19 |
| 11467972 | L1D to L2 eviction | Colin Eddy | 2022-10-11 |
| 11061853 | Processor with memory controller including dynamically programmable functional unit | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2021-07-13 |
| 11029949 | Neural network unit | G. Glenn Henry, Kim C. Houck, Parviz Palangpour | 2021-06-08 |
| 10725934 | Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode | G. Glenn Henry, Terry Parks | 2020-07-28 |
| 10719434 | Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode | — | 2020-07-21 |
| 10698827 | Dynamic cache replacement way selection based on address tag bits | — | 2020-06-30 |
| 10664751 | Processor with memory array operable as either cache memory or neural network unit memory | G. Glenn Henry | 2020-05-26 |
| 10642617 | Processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2020-05-05 |
| 10430706 | Processor with memory array operable as either last level cache slice or neural network unit memory | G. Glenn Henry | 2019-10-01 |
| 10423876 | Processor with memory array operable as either victim cache or neural network unit memory | G. Glenn Henry | 2019-09-24 |
| 10387318 | Prefetching with level of aggressiveness based on effectiveness by memory access type | Rodney E. Hooker, John Michael Greer, Colin Eddy | 2019-08-20 |
| 10324842 | Distributed hang recovery logic | — | 2019-06-18 |
| 10268587 | Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2019-04-23 |
| 10268586 | Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2019-04-23 |
| 10146543 | Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2018-12-04 |
| 10127041 | Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Rodney E. Hooker, Terry Parks | 2018-11-13 |
| 10073787 | Dynamic powering of cache memory by ways within multiple set groups based on utilization trends | Rodney E. Hooker | 2018-09-11 |
| 10067871 | Logic analyzer for detecting hangs | Rodney E. Hooker | 2018-09-04 |
| 9972375 | Sanitize-aware DRAM controller | Terry Parks, Rodney E. Hooker | 2018-05-15 |
| 9946651 | Pattern detector for detecting hangs | Rodney E. Hooker | 2018-04-17 |