Issued Patents All Time
Showing 26–50 of 277 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10346351 | Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network LSTM cells | G. Glenn Henry, Kyle T. O'Brien | 2019-07-09 |
| 10346350 | Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor | G. Glenn Henry | 2019-07-09 |
| 10282348 | Neural network unit with output buffer feedback and masking capability | G. Glenn Henry, Kyle T. O'Brien | 2019-05-07 |
| 10275394 | Processor with architectural neural network execution unit | G. Glenn Henry | 2019-04-30 |
| 10275393 | Tri-configuration neural network unit | G. Glenn Henry | 2019-04-30 |
| 10268587 | Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests | G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed | 2019-04-23 |
| 10268586 | Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests | G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed | 2019-04-23 |
| 10235232 | Processor with approximate computing execution unit that includes an approximation control register having an approximation mode flag, an approximation amount, and an error threshold, where the approximation control register is writable by an instruction set instruction | G. Glenn Henry, Rodney E. Hooker | 2019-03-19 |
| 10228911 | Apparatus employing user-specified binary point fixed point arithmetic | G. Glenn Henry | 2019-03-12 |
| 10216520 | Compressing instruction queue for a microprocessor | Matthew Daniel Day, G. Glenn Henry | 2019-02-26 |
| 10198269 | Dynamic reconfiguration of multi-core processor | G. Glenn Henry, Darius D. Gaskins | 2019-02-05 |
| 10146543 | Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed | 2018-12-04 |
| 10127041 | Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources | G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed | 2018-11-13 |
| 10108431 | Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state | G. Glenn Henry, Brent Bean, Stephan Gaskins | 2018-10-23 |
| 10019260 | Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match | G. Glenn Henry, Rodney E. Hooker, Colin Eddy | 2018-07-10 |
| 9972375 | Sanitize-aware DRAM controller | Rodney E. Hooker, Douglas R. Reed | 2018-05-15 |
| 9967092 | Key expansion logic using decryption key primitives | G. Glenn Henry, Brent Bean, Thomas A. Crispin | 2018-05-08 |
| 9952654 | Centralized synchronization mechanism for a multi-core processor | G. Glenn Henry | 2018-04-24 |
| 9911008 | Microprocessor with on-the-fly switching of decryption keys | G. Glenn Henry, Brent Bean, Thomas A. Crispin | 2018-03-06 |
| 9898303 | Multi-core hardware semaphore in non-architectural address space | G. Glenn Henry | 2018-02-20 |
| 9898291 | Microprocessor with arm and X86 instruction length decoders | G. Glenn Henry, Rodney E. Hooker | 2018-02-20 |
| 9892283 | Decryption of encrypted instructions using keys selected on basis of instruction fetch address | G. Glenn Henry, Brent Bean, Thomas A. Crispin | 2018-02-13 |
| 9891927 | Inter-core communication via uncore RAM | G. Glenn Henry, Rodney E. Hooker, Stephan Gaskins | 2018-02-13 |
| 9891918 | Fractional use of prediction history storage for operating system routines | Rodney E. Hooker, John Bunda | 2018-02-13 |
| 9830155 | Microprocessor using compressed and uncompressed microcode storage | G. Glenn Henry, Brent Bean | 2017-11-28 |