Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10204056 | Dynamic cache enlarging by counting evictions | G. Glenn Henry | 2019-02-12 |
| 10108431 | Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state | G. Glenn Henry, Terry Parks, Brent Bean | 2018-10-23 |
| 9971605 | Selective designation of multiple cores as bootstrap processor in a multi-core microprocessor | G. Glenn Henry | 2018-05-15 |
| 9911508 | Cache memory diagnostic writeback | Rodney E. Hooker, Douglas R. Reed, Jason Chen | 2018-03-06 |
| 9891927 | Inter-core communication via uncore RAM | G. Glenn Henry, Terry Parks, Rodney E. Hooker | 2018-02-13 |
| 9891928 | Propagation of updates to per-core-instantiated architecturally-visible storage resource | G. Glenn Henry | 2018-02-13 |
| 9811344 | Core ID designation system for dynamically designated bootstrap processor | G. Glenn Henry | 2017-11-07 |
| 9792112 | Propagation of microcode patches to multiple cores in multicore microprocessor | G. Glenn Henry | 2017-10-17 |
| 9690511 | Multi-core data array power gating restoral mechanism | G. Glenn Henry, Dinesh K. Jain | 2017-06-27 |
| 9665490 | Apparatus and method for repairing cache arrays in a multi-core microprocessor | G. Glenn Henry, Dinesh K. Jain | 2017-05-30 |
| 9606933 | Multi-core apparatus and method for restoring data arrays following a power gating event | G. Glenn Henry, Dinesh K. Jain | 2017-03-28 |
| 9594690 | Multi-core microprocessor power gating cache restoral programming mechanism | G. Glenn Henry, Dinesh K. Jain | 2017-03-14 |
| 9594691 | Multi-core programming apparatus and method for restoring data arrays following a power gating event | G. Glenn Henry, Dinesh K. Jain | 2017-03-14 |
| 9582429 | Multi-core data array power gating cache restoral programming mechanism | G. Glenn Henry, Dinesh K. Jain | 2017-02-28 |
| 9582428 | Multi-core programming apparatus and method for restoring data arrays following a power gating event | G. Glenn Henry, Dinesh K. Jain | 2017-02-28 |
| 9575541 | Propagation of updates to per-core-instantiated architecturally-visible storage resource | G. Glenn Henry | 2017-02-21 |
| 9535488 | Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor | G. Glenn Henry | 2017-01-03 |
| 9524241 | Multi-core microprocessor power gating cache restoral mechanism | G. Glenn Henry, Dinesh K. Jain | 2016-12-20 |
| 9507404 | Single core wakeup multi-core synchronization mechanism | G. Glenn Henry, Terry Parks, Brent Bean | 2016-11-29 |
| 9471133 | Service processor patch mechanism | G. Glenn Henry | 2016-10-18 |
| 9395802 | Multi-core data array power gating restoral mechanism | G. Glenn Henry, Dinesh K. Jain | 2016-07-19 |
| 9367497 | Reconfigurably designating master core for conditional output on sideband communication wires distinct from system bus | G. Glenn Henry | 2016-06-14 |
| 8972707 | Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin | G. Glenn Henry | 2015-03-03 |
| 8935549 | Microprocessor with multicore processor power credit management feature | G. Glenn Henry, Darius D. Gaskins | 2015-01-13 |
| 8914661 | Multicore processor power credit management in which multiple processing cores use shared memory to communicate individual energy consumption | G. Glenn Henry, Darius D. Gaskins | 2014-12-16 |