Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11567776 | Branch density detection for prefetcher | Thomas C. McDonald | 2023-01-31 |
| 10108431 | Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state | G. Glenn Henry, Terry Parks, Stephan Gaskins | 2018-10-23 |
| 10078581 | Processor with instruction cache that performs zero clock retires | — | 2018-09-18 |
| 10067875 | Processor with instruction cache that performs zero clock retires | — | 2018-09-04 |
| 9967092 | Key expansion logic using decryption key primitives | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2018-05-08 |
| 9911008 | Microprocessor with on-the-fly switching of decryption keys | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2018-03-06 |
| 9892283 | Decryption of encrypted instructions using keys selected on basis of instruction fetch address | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2018-02-13 |
| 9830155 | Microprocessor using compressed and uncompressed microcode storage | G. Glenn Henry, Terry Parks | 2017-11-28 |
| 9798675 | System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions | Colin Eddy | 2017-10-24 |
| 9798669 | System and method of determining memory ownership on cache line basis for detecting self-modifying code | Colin Eddy | 2017-10-24 |
| 9798670 | System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction | Colin Eddy | 2017-10-24 |
| 9798898 | Microprocessor with secure execution mode and store key instructions | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2017-10-24 |
| 9792216 | System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries | Colin Eddy | 2017-10-17 |
| 9507404 | Single core wakeup multi-core synchronization mechanism | G. Glenn Henry, Terry Parks, Stephan Gaskins | 2016-11-29 |
| 9483263 | Uncore microcode ROM | G. Glenn Henry, Terry Parks, Rodney E. Hooker, John Bunda | 2016-11-01 |
| 9461818 | Method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2016-10-04 |
| 9372696 | Microprocessor with compressed and uncompressed microcode memories | G. Glenn Henry, Terry Parks | 2016-06-21 |
| 9361097 | Selectively compressed microcode | G. Glenn Henry, Terry Parks | 2016-06-07 |
| 8886960 | Microprocessor that facilitates task switching between encrypted and unencrypted programs | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2014-11-11 |
| 8880902 | Microprocessor that securely decrypts and executes encrypted instructions | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2014-11-04 |
| 8850229 | Apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2014-09-30 |
| 8719589 | Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key values | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2014-05-06 |
| 8700919 | Switch key instruction in a microprocessor that fetches and decrypts encrypted instructions | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2014-04-15 |
| 8683225 | Microprocessor that facilitates task switching between encrypted and unencrypted programs | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2014-03-25 |
| 8671285 | Microprocessor that fetches and decrypts encrypted instructions in same time as plain text instructions | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2014-03-11 |