Issued Patents All Time
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8645714 | Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2014-02-04 |
| 8639945 | Branch and switch key instruction in a microprocessor that fetches and decrypts encrypted instructions | G. Glenn Henry, Terry Parks, Thomas A. Crispin | 2014-01-28 |
| 8635437 | Pipelined microprocessor with fast conditional branch instructions based on static exception state | G. Glenn Henry, Terry Parks | 2014-01-21 |
| 8521996 | Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution | G. Glenn Henry, Terry Parks | 2013-08-27 |
| 8423751 | Microprocessor with fast execution of call and return instructions | G. Glenn Henry, Terry Parks | 2013-04-16 |
| 8281110 | Out-of-order microprocessor with separate branch information circular queue table tagged by branch instructions in reorder buffer to reduce unnecessary space in buffer | Thomas C. McDonald | 2012-10-02 |
| 8245017 | Pipelined microprocessor with normal and fast conditional branch instructions | G. Glenn Henry, Terry Parks | 2012-08-14 |
| 8145890 | Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state | G. Glenn Henry, Terry Parks | 2012-03-27 |
| 8131984 | Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state | G. Glenn Henry, Terry Parks | 2012-03-06 |
| 8074060 | Out-of-order execution microprocessor that selectively initiates instruction retirement early | Gerard M. Col, Bryan Wayne Pogor | 2011-12-06 |
| 7979675 | Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution | G. Glenn Henry, Terry Parks | 2011-07-12 |
| 7975132 | Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor | Terry Parks, G. Glenn Henry | 2011-07-05 |
| 7234045 | Apparatus and method for handling BTAC branches that wrap across instruction cache lines | G. Glenn Henry, Thomas C. McDonald | 2007-06-19 |
| 7203824 | Apparatus and method for handling BTAC branches that wrap across instruction cache lines | G. Glenn Henry, Thomas C. McDonald | 2007-04-10 |
| 5319213 | Thermal target test board | Wendell R. Watkins, Peter D. Munding | 1994-06-07 |