Issued Patents All Time
Showing 26–50 of 140 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9891918 | Fractional use of prediction history storage for operating system routines | Terry Parks, John Bunda | 2018-02-13 |
| 9817764 | Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type | Douglas R. Reed, John Michael Greer, Colin Eddy | 2017-11-14 |
| 9811468 | Set associative cache memory with heterogeneous replacement policy | Douglas R. Reed, John Michael Greer, Colin Eddy | 2017-11-07 |
| 9753799 | Conditional pattern detector for detecting hangs | Douglas R. Reed | 2017-09-05 |
| 9755902 | Dynamic system configuration based on cloud-collaborative experimentation | Wen-Chi Chen | 2017-09-05 |
| 9652400 | Fully associative cache memory budgeted by memory access type | Douglas R. Reed, John Michael Greer, Colin Eddy, Albert J. Loper | 2017-05-16 |
| 9652398 | Cache replacement policy that considers memory access type | Douglas R. Reed, John Michael Greer, Colin Eddy, Terry Parks | 2017-05-16 |
| 9645822 | Conditional store instructions in an out-of-order execution microprocessor | G. Glenn Henry, Terry Parks, Gerard M. Col, Colin Eddy | 2017-05-09 |
| 9588845 | Processor that recovers from excessive approximate computing error | G. Glenn Henry, Terry Parks | 2017-03-07 |
| 9575778 | Dynamically configurable system based on cloud-collaborative experimentation | Wen-Chi Chen | 2017-02-21 |
| 9575816 | Deadlock/livelock resolution using service processor | Douglas R. Reed | 2017-02-21 |
| 9569363 | Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry | Colin Eddy | 2017-02-14 |
| 9507597 | Selective accumulation and use of predicting unit history | Terry Parks, John Michael Greer | 2016-11-29 |
| 9501286 | Microprocessor with ALU integrated into load unit | Gerard M. Col, Colin Eddy | 2016-11-22 |
| 9483406 | Communicating prefetchers that throttle one another | John Michael Greer | 2016-11-01 |
| 9483263 | Uncore microcode ROM | G. Glenn Henry, Terry Parks, John Bunda, Brent Bean | 2016-11-01 |
| 9389863 | Processor that performs approximate computing instructions | G. Glenn Henry, Terry Parks | 2016-07-12 |
| 9378019 | Conditional load instructions in an out-of-order execution microprocessor | G. Glenn Henry, Terry Parks, Gerard M. Col, Colin Eddy | 2016-06-28 |
| 9317301 | Microprocessor with boot indicator that indicates a boot ISA of the microprocessor as either the X86 ISA or the ARM ISA | G. Glenn Henry, Terry Parks | 2016-04-19 |
| 9317288 | Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline | G. Glenn Henry, Terry Parks | 2016-04-19 |
| 9274795 | Conditional non-branch instruction prediction | G. Glenn Henry, Terry Parks | 2016-03-01 |
| 9251083 | Communicating prefetchers in a microprocessor | John Michael Greer | 2016-02-02 |
| 9244686 | Microprocessor that translates conditional load/store instructions into variable number of microinstructions | G. Glenn Henry, Terry Parks, Gerard M. Col, Colin Eddy | 2016-01-26 |
| 9176733 | Load multiple and store multiple instructions in a microprocessor that emulates banked registers | G. Glenn Henry, Terry Parks | 2015-11-03 |
| 9146742 | Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA | G. Glenn Henry, Terry Parks | 2015-09-29 |