Issued Patents All Time
Showing 76–100 of 140 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8392693 | Fast REP STOS using grabline operations | G. Glenn Henry, Colin Eddy | 2013-03-05 |
| 8392666 | Low power high speed load-store collision detector | Colin Eddy | 2013-03-05 |
| 8364902 | Microprocessor with repeat prefetch indirect instruction | John Michael Greer | 2013-01-29 |
| 8364906 | Avoiding memory access latency by returning hit-modified when holding non-modified data | Colin Eddy, Darius D. Gaskins, Albert J. Loper | 2013-01-29 |
| 8301842 | Efficient pseudo-LRU for colliding accesses | Colin Eddy | 2012-10-30 |
| 8291172 | Multi-modal data prefetcher | Colin Eddy | 2012-10-16 |
| 8234450 | Efficient data prefetching in the presence of load hits | Clinton Thomas Glover, Colin Eddy, Albert J. Loper | 2012-07-31 |
| 8161246 | Prefetching of next physically sequential cache line after cache line that includes loaded page table entry | Colin Eddy | 2012-04-17 |
| 8108624 | Data cache with modified bit array | Colin Eddy, G. Glenn Henry | 2012-01-31 |
| 8108621 | Data cache with modified bit array | Colin Eddy, G. Glenn Henry | 2012-01-31 |
| 8090931 | Microprocessor with fused store address/store data microinstruction | Gerard M. Col, G. Glenn Henry, Terry Parks | 2012-01-03 |
| 8069340 | Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions | Gerard M. Col, Colin Eddy | 2011-11-29 |
| 7996650 | Microprocessor that performs speculative tablewalks | Colin Eddy | 2011-08-09 |
| 7827390 | Microprocessor with private microcode RAM | G. Glenn Henry, Colin Eddy, Terry Parks | 2010-11-02 |
| 7647478 | Suppression of store checking | G. Glenn Henry, Terry Parks | 2010-01-12 |
| 7647479 | Non-temporal memory reference control mechanism | G. Glenn Henry, Terry Parks | 2010-01-12 |
| 7562192 | Microprocessor, apparatus and method for selective prefetch retire | G. Glenn Henry | 2009-07-14 |
| 7546446 | Selective interrupt suppression | Glenn Henry, Terry Parks | 2009-06-09 |
| 7543134 | Apparatus and method for extending a microprocessor instruction set | G. Glenn Henry, Terry Parks | 2009-06-02 |
| 7529912 | Apparatus and method for instruction-level specification of floating point format | G. Glenn Henry, Terry Parks | 2009-05-05 |
| 7395412 | Apparatus and method for extending data modes in a microprocessor | G. Glenn Henry, Terry Parks | 2008-07-01 |
| 7383394 | Microprocessor, apparatus and method for selective prefetch retire | G. Glenn Henry | 2008-06-03 |
| 7380103 | Apparatus and method for selective control of results write back | G. Glenn Henry, Terry Parks | 2008-05-27 |
| 7380109 | Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor | G. Glenn Henry, Terry Parks | 2008-05-27 |
| 7373483 | Mechanism for extending the number of registers in a microprocessor | G. Glenn Henry, Terry Parks | 2008-05-13 |