Issued Patents All Time
Showing 51–75 of 140 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9141389 | Heterogeneous ISA microprocessor with shared hardware ISA registers | G. Glenn Henry, Terry Parks | 2015-09-22 |
| 9128701 | Generating constant for microinstructions from modified immediate field during instruction translation | G. Glenn Henry, Terry Parks | 2015-09-08 |
| 9043580 | Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA) | G. Glenn Henry, Terry Parks | 2015-05-26 |
| 9032189 | Efficient conditional ALU instruction in read-port limited register file microprocessor | G. Glenn Henry, Gerard M. Col, Terry Parks | 2015-05-12 |
| 8930679 | Out-of-order execution microprocessor with reduced store collision load replay by making an issuing of a load instruction dependent upon a dependee instruction of a store instruction | Matthew Daniel Day | 2015-01-06 |
| 8924695 | Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor | G. Glenn Henry, Gerard M. Col, Terry Parks | 2014-12-30 |
| 8909908 | Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instruction | Gerard M. Col, Bryan Wayne Pogor | 2014-12-09 |
| 8880854 | Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register | Gerard M. Col, Terry Parks | 2014-11-04 |
| 8880807 | Bounding box prefetcher | John Michael Greer | 2014-11-04 |
| 8880851 | Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline | G. Glenn Henry, Terry Parks | 2014-11-04 |
| 8880857 | Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor | G. Glenn Henry, Gerard M. Col, Terry Parks | 2014-11-04 |
| 8782348 | Microprocessor cache line evict array | Colin Eddy | 2014-07-15 |
| 8762779 | Multi-core processor with external instruction execution rate heartbeat | Darius D. Gaskins, Jason Chen | 2014-06-24 |
| 8762649 | Bounding box prefetcher | John Michael Greer | 2014-06-24 |
| 8719510 | Bounding box prefetcher with reduced warm-up penalty on memory block crossings | John Michael Greer | 2014-05-06 |
| 8645631 | Combined L2 cache and L1D cache prefetcher | John Michael Greer | 2014-02-04 |
| 8595471 | Executing repeat load string instruction with guaranteed prefetch microcode to prefetch into cache for loading up to the last value in architectural register | G. Glenn Henry | 2013-11-26 |
| 8566565 | Microprocessor with multiple operating modes dynamically configurable by a device driver based on currently running applications | Colin Eddy, G. Glenn Henry | 2013-10-22 |
| 8543765 | Efficient data prefetching in the presence of load hits | Clinton Thomas Glover, Colin Eddy, Albert J. Loper | 2013-09-24 |
| 8533438 | Store-to-load forwarding based on load/store address computation source information comparisons | Colin Eddy | 2013-09-10 |
| 8533437 | Guaranteed prefetch instruction | G. Glenn Henry, Colin Eddy | 2013-09-10 |
| 8495343 | Apparatus and method for detection and correction of denormal speculative floating point operand | G. Glenn Henry, Gerard M. Col, Timothy A. Elliott, Terry Parks | 2013-07-23 |
| 8489823 | Efficient data prefetching in the presence of load hits | Clinton Thomas Glover, Colin Eddy, Albert J. Loper | 2013-07-16 |
| 8464029 | Out-of-order execution microprocessor with reduced store collision load replay reduction | Matthew Daniel Day | 2013-06-11 |
| 8433853 | Prefetching of next physically sequential cache line after cache line that includes loaded page table entry | Colin Eddy | 2013-04-30 |