Issued Patents All Time
Showing 101–125 of 184 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5924006 | Trench surrounded metal pattern | Chen-Chiu Hsue, Hong J. Wu | 1999-07-13 |
| 5915201 | Trench surrounded metal pattern | Peter Chang, Chen-Chiu Hsue | 1999-06-22 |
| 5913124 | Method of making a self-aligned silicide | Tony Lin | 1999-06-15 |
| 5902752 | Active layer mask with dummy pattern | Shin-Wei Sun, Ming-Tzong Yang, Hong-Tsz Pan | 1999-05-11 |
| 5895252 | Field oxidation by implanted oxygen (FIMOX) | Cheng-Han Huang | 1999-04-20 |
| 5895254 | Method of manufacturing shallow trench isolation structure | Kuo-Tai Huang, Tony Lin | 1999-04-20 |
| 5885894 | Method of planarizing an inter-layer dielectric layer | Jiunh-Yuan Wu, Shih-Wei Sun | 1999-03-23 |
| 5874353 | Method of forming a self-aligned silicide device | Tony Lin, Shih-Wei Sun | 1999-02-23 |
| 5869368 | Method to increase capacitance | Tri-Rung Yew, Shih-Wei Sun | 1999-02-09 |
| 5828134 | Metallization to improve electromigration resistance | Jiun-Yuan Wu | 1998-10-27 |
| 5828121 | Multi-level conduction structure for VLSI circuits | Jiunn Y. Wu | 1998-10-27 |
| 5801094 | Dual damascene process | Tri-Rung Yew, Meng-Chang Liu, Shih-Wei Sun | 1998-09-01 |
| 5780348 | Method of making a self-aligned silicide component | Tony Lin, Shih-Wei Sun | 1998-07-14 |
| 5753559 | Method for growing hemispherical grain silicon | Tri-Rung Yew, Shih-Wei Sun | 1998-05-19 |
| 5739046 | Method of making a reliable barrier layer | Shih-Chanh Chang, Jiun-Yuan Wu, Der-Yuan Wu | 1998-04-14 |
| 5716888 | Stress released VLSI structure by void formation | Jenn-Tarng Lin, Her-Song Liaw | 1998-02-10 |
| 5712185 | Method for forming shallow trench isolation | Meng-Jin Tsai, Chin-Lai Chen | 1998-01-27 |
| 5674354 | Method for etching a conducting layer of the step-covered structure for semiconductor fabrication | Anna Su | 1997-10-07 |
| 5668394 | Prevention of fluorine-induced gate oxide degradation in WSi polycide structure | Cheng-Han Huang | 1997-09-16 |
| 5668393 | Locos technology with reduced junction leakage | Der-Yuan Wu, Jiunn Y. Wu | 1997-09-16 |
| 5665632 | Stress relaxation in dielectric before metalization | Edward Houn | 1997-09-09 |
| 5663599 | Metal layout pattern for improved passivation layer coverage | — | 1997-09-02 |
| 5661049 | Stress relaxation in dielectric before metallization | Edward Houn | 1997-08-26 |
| 5640041 | Stress relaxation in dielectric before metallization | Edward Houn | 1997-06-17 |
| 5633197 | Metallization to improve electromigration resistance by etching concavo-concave opening | Jiun-Yuan Wu | 1997-05-27 |