Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5828121 | Multi-level conduction structure for VLSI circuits | Water Lur | 1998-10-27 |
| 5668393 | Locos technology with reduced junction leakage | Water Lur, Der-Yuan Wu | 1997-09-16 |
| 5529948 | LOCOS technology with reduced junction leakage | Water Lur, Dey Y. Wu | 1996-06-25 |
| 5512768 | Capacitor for use in DRAM cell using surface oxidized silicon nodules | Water Lur, Johnson Liu | 1996-04-30 |
| 5492848 | Stacked capacitor process using silicon nodules | Water Lur, Cheng-Hen Huang | 1996-02-20 |
| 5482882 | Method for forming most capacitor using polysilicon islands | Water Lur, Pin-I Chen | 1996-01-09 |
| 5432073 | Method for metal deposition without poison via | Water Lur | 1995-07-11 |
| 5413962 | Multi-level conductor process in VLSI fabrication utilizing an air bridge | Water Lur | 1995-05-09 |
| 5366925 | Local oxidation of silicon by using aluminum spiking technology | Water Lur, Shim F. Tzou | 1994-11-22 |
| 5308786 | Trench isolation for both large and small areas by means of silicon nodules after metal etching | Water Lur, Anna Su | 1994-05-03 |