Issued Patents All Time
Showing 51–75 of 184 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6218284 | Method for forming an inter-metal dielectric layer | Chih-Chien Liu, Cheng-Yuan Tsai, Wen-Yi Hsieh | 2001-04-17 |
| 6214691 | Method for forming shallow trench isolation | Gwo-Shii Yong, Chih-Chien Liu, Tri-Rung Yew | 2001-04-10 |
| 6214745 | Method of improving surface planarity of chemical-mechanical polishing operation by forming shallow dummy pattern | Ming-Sheng Yang, Yimin Huang, Juan-Yuan Wu | 2001-04-10 |
| 6203863 | Method of gap filling | Chih-Chien Liu, Juan-Yuan Wu, Shih-Wei Sun | 2001-03-20 |
| 6180451 | Method of forming capacitor with a HSG layer | Wen-Yi Hsieh, Juan-Yuan Wu | 2001-01-30 |
| 6180492 | Method of forming a liner for shallow trench isolation | Hsueh-Hao Shih, Tri-Rung Yew, Gwo-Shii Yang | 2001-01-30 |
| 6178543 | Method of designing active region pattern with shift dummy pattern | Coming Chen, Juan-Yuan Wu | 2001-01-23 |
| 6174812 | Copper damascene technology for ultra large scale integration circuits | Chiung-Sheng Hsiung, Wen-Yi Hsieh | 2001-01-16 |
| 6171899 | Method for fabricating a capacitor | Fu-Tai Liou, Kuan-Cheng Su, Juan-Yuan Wu | 2001-01-09 |
| 6169012 | Chemical mechanical polishing for forming a shallow trench isolation structure | Coming Chen, Juan-Yuan Wu | 2001-01-02 |
| 6159845 | Method for manufacturing dielectric layer | Tri-Rung Yew, Hsien-Ta Chung | 2000-12-12 |
| 6156642 | Method of fabricating a dual damascene structure in an integrated circuit | Juan-Yuan Wu | 2000-12-05 |
| 6156671 | Method for improving characteristic of dielectric material | Ting-Chang Chang, Po-Tsun Liu | 2000-12-05 |
| 6153466 | Method for increasing capacitance | Tri-Rung Yew, Shih-Wei Sun | 2000-11-28 |
| 6150251 | Method of fabricating gate | Tri-Rung Yew | 2000-11-21 |
| 6140227 | Method of fabricating a glue layer of contact/via | Coming Chen | 2000-10-31 |
| 6136713 | Method for forming a shallow trench isolation structure | Coming Chen, Jenn Tsao | 2000-10-24 |
| 6117345 | High density plasma chemical vapor deposition process | Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Shih-Wei Sun | 2000-09-12 |
| 6114200 | Method of fabricating a dynamic random access memory device | Tri-Rung Yew, Shih-Wei Sun | 2000-09-05 |
| 6099705 | Physical vapor deposition device for forming a uniform metal layer on a semiconductor wafer | Hsueh-Chung Chen, Juan-Yuan Wu | 2000-08-08 |
| 6100191 | Method for forming self-aligned silicide layers on sub-quarter micron VLSI circuits | Tony Lin, Jiun-Yuan Wu, Hsiao-Lin Lu | 2000-08-08 |
| 6100205 | Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process | Chih-Chien Liu, J. Y. Wu, Tsang-Jung Lin, Shih-Wei Sun | 2000-08-08 |
| 6097093 | Structure of a dual damascene | Juan-Yuan Wu | 2000-08-01 |
| 6093089 | Apparatus for controlling uniformity of polished material | Hsueh-Chung Chen, Juan-Yuan Wu | 2000-07-25 |
| 6087262 | Method for manufacturing shallow trench isolation structure | Gwo-Shii Yang, Kuo-Tai Huang, Tri-Rung Yew | 2000-07-11 |