Issued Patents All Time
Showing 151–175 of 184 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5460987 | Method of making field effect transistor structure of a diving channel device | Jemmy Wen, Joe Ko | 1995-10-24 |
| 5459095 | Method for making capacitor for use in DRAM cell using triple layers of photoresist | Cheng-Han Huang | 1995-10-17 |
| 5457065 | method of manufacturing a new DRAM capacitor structure having increased capacitance | Cheng-Han Huang | 1995-10-10 |
| 5453395 | Isolation technology using liquid phase deposition | — | 1995-09-26 |
| 5451804 | VLSI device with global planarization | Ben Chen | 1995-09-19 |
| 5449630 | Method for fabricating a trench capacitor structure for dynamic random access memory integrated circuit | Cheng-Han Huang | 1995-09-12 |
| 5445989 | Method of forming device isolation regions | Po-Wen Yen | 1995-08-29 |
| 5438015 | Silicon-on-insulator technique with buried gap | — | 1995-08-01 |
| 5432073 | Method for metal deposition without poison via | Jiunn Y. Wu | 1995-07-11 |
| 5428240 | Source/drain structural configuration for MOSFET integrated circuit devices | — | 1995-06-27 |
| 5427974 | Method for forming a capacitor in a DRAM cell using a rough overlayer of tungsten | Chang-Shyan Kao, Peter Lin | 1995-06-27 |
| 5422312 | Method for forming metal via | David Lee | 1995-06-06 |
| 5413962 | Multi-level conductor process in VLSI fabrication utilizing an air bridge | Jiunn Y. Wu | 1995-05-09 |
| 5395790 | Stress-free isolation layer | — | 1995-03-07 |
| 5393709 | Method of making stress released VLSI structure by the formation of porous intermetal layer | J. Y. Wu | 1995-02-28 |
| 5393704 | Self-aligned trenched contact (satc) process | Cheng-Han Huang | 1995-02-28 |
| 5391519 | Method for increasing pad bonding of an IC (1) | Ming-Tsung Liu, Der-Yuan Wu | 1995-02-21 |
| 5384268 | Charge damage free implantation by introduction of a thin conductive layer | Ben Chen, Cheng-Han Huang | 1995-01-24 |
| 5380671 | Method of making non-trenched buried contact for VLSI devices | D. Y. Wu | 1995-01-10 |
| 5374583 | Technology for local oxidation of silicon | Jiun-Yuan Wu, Anna Su | 1994-12-20 |
| 5374586 | Multi-LOCOS (local oxidation of silicon) isolation process | Cheng-Han Huang | 1994-12-20 |
| 5372968 | Planarized local oxidation by trench-around technology | Anna Su, Neng-Hsing Shen | 1994-12-13 |
| 5371036 | Locos technology with narrow silicon trench | Cheng-Han Huang | 1994-12-06 |
| 5366911 | VLSI process with global planarization | Ben Chen | 1994-11-22 |
| 5366925 | Local oxidation of silicon by using aluminum spiking technology | Jiunn Y. Wu, Shim F. Tzou | 1994-11-22 |