Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5864163 | Fabrication of buried channel devices with shallow junction depth | Jih-Wen Chou | 1999-01-26 |
| 5811283 | Silicon on insulator (SOI) dram cell structure and process | — | 1998-09-22 |
| 5801094 | Dual damascene process | Tri-Rung Yew, Meng-Chang Liu, Water Lur | 1998-09-01 |
| 5789290 | Polysilicon CMP process for high-density DRAM cell structures | — | 1998-08-04 |
| 5780348 | Method of making a self-aligned silicide component | Tony Lin, Water Lur | 1998-07-14 |
| 5753559 | Method for growing hemispherical grain silicon | Tri-Rung Yew, Water Lur | 1998-05-19 |
| 5744841 | Semiconductor device with ESD protection | Percy V. Gilbert, Paul G. Y. Tsui, Stephen G. Jamison | 1998-04-28 |
| 5733794 | Process for forming a semiconductor device with ESD protection | Percy V. Gilbert, Paul G. Y. Tsui, Stephen G. Jamison | 1998-03-31 |
| 5708288 | Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method | John H. Quigley, Jeremy C. Smith, Percy V. Gilbert | 1998-01-13 |
| 5670387 | Process for forming semiconductor-on-insulator device | — | 1997-09-23 |
| 5605855 | Process for fabricating a graded-channel MOS device | Ko-Min Chang, Marius Orlowski, Craig T. Swift, Shiang-Chyong Luo | 1997-02-25 |
| 5552332 | Process for fabricating a MOSFET device having reduced reverse short channel effects | Hsing-Huang Tseng, Philip J. Tobin, Paul G. Y. Tsui, Stephen S. Poon | 1996-09-03 |
| 5545574 | Process for forming a semiconductor device having a metal-semiconductor compound | Wei-Ming Chen, Paul G. Y. Tsui | 1996-08-13 |
| 5496764 | Process for forming a semiconductor region adjacent to an insulating layer | — | 1996-03-05 |
| 5406111 | Protection device for an intergrated circuit and method of formation | — | 1995-04-11 |
| 5399507 | Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications | — | 1995-03-21 |
| 5381040 | Small geometry contact | Michael P. Woo | 1995-01-10 |
| 5369052 | Method of forming dual field oxide isolation | Prashant U. Kenkare, James R. Pfiester | 1994-11-29 |
| 5345105 | Structure for shielding conductors | Yasunobu Kosa, John R. Yeargain | 1994-09-06 |
| 5279990 | Method of making a small geometry contact using sidewall spacers | Michael P. Woo | 1994-01-18 |
| 5262353 | Process for forming a structure which electrically shields conductors | Yasunobu Kosa, John R. Yeargain | 1993-11-16 |
| 5034351 | Process for forming a feature on a substrate without recessing the surface of the substrate | Michael P. Woo | 1991-07-23 |
| 4994410 | Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process | Jen-Jiang Lee | 1991-02-19 |
| 4926237 | Device metallization, device and method | Jen-Jiang Lee | 1990-05-15 |
| 4897364 | Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer | Bich-Yen Nguyen, Philip J. Tobin, Michael P. Woo | 1990-01-30 |