Issued Patents All Time
Showing 201–225 of 244 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7227218 | Method and system for forming source regions in memory devices | Yi-Shing Chang | 2007-06-05 |
| 7153755 | Process to improve programming of memory cells | Shih-Chang Liu, Chien-Ming Ku, Chi-Hsin Lo, Chia-Shiung Tsai, Chia-Ta Hsieh | 2006-12-26 |
| 7106629 | Split-gate P-channel flash memory cell with programming by band-to-band hot electron method | Chia-Ta Hsieh | 2006-09-12 |
| 7030444 | Space process to prevent the reverse tunneling in split gate flash | Kuo-Chi Tu, Yi-Shing Chang, Yi-Jiun Lin | 2006-04-18 |
| 7022592 | Ammonia-treated polysilicon semiconductor device | Yeur-Luen Tu | 2006-04-04 |
| 6982458 | Method of making the selection gate in a split-gate flash EEPROM cell and its structure | Jack Y. Yeh, Chrong-Jung Lin | 2006-01-03 |
| 6933198 | Method for forming enhanced areal density split gate field effect transistor device array | Chia-Ta Hsieh, Chrong-Jung Lin | 2005-08-23 |
| 6924199 | Method to form flash memory with very narrow polysilicon spacing | Shih-Chang Liu | 2005-08-02 |
| 6902978 | Method of making the selection gate in a split-gate flash EEPROM cell and its structure | Jack Y. Yeh, Chrong-Jung Lin | 2005-06-07 |
| 6890821 | Method and system for forming source regions in memory devices | Yi-Shing Chang | 2005-05-10 |
| 6855602 | Method for forming a box shaped polygate | Yi-Shing Chang, Yeur-Luen Tu, Chia-Shiung Tsai | 2005-02-15 |
| 6803625 | Method with trench source to increase the coupling of source to floating gate in split gate flash | Chia-Ta Hsieh, Di-Son Kuo, Chrong-Jun Lin | 2004-10-12 |
| 6787418 | Method of making the selection gate in a split-gate flash eeprom cell and its structure | Jack Y. Yeh, Chrong-Jung Lin | 2004-09-07 |
| 6624025 | Method with trench source to increase the coupling of source to floating gate in split gate flash | Chia-Ta Hsieh, Di-Son Kuo, Chrong-Jun Lin | 2003-09-23 |
| 6544828 | Adding a poly-strip on isolation's edge to improve endurance of high voltage NMOS on EEPROM | Di-Son Kuo, Jack Y. Yeh, Chia-Ta Hsieh, Chrong-Jung Lin, Sheng-Wei Tsaur | 2003-04-08 |
| 6538277 | Split-gate flash cell | Hung-Cheng Sung, Di-Son Kuo, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin | 2003-03-25 |
| 6534821 | Structure with protruding source in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo | 2003-03-18 |
| 6479859 | Split gate flash memory with multiple self-alignments | Chia-Ta Hsieh, Tai-Fen Lin, Chuang-Ke Yeh, Hung-Cheng Sung, Di-Son Kuo | 2002-11-12 |
| 6468863 | Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof | Chia-Ta Hsieh, Di-Son Kuo, Jake Yeh, Chuan-Li Chang, Sheng-Wei Tsaur | 2002-10-22 |
| 6465836 | Vertical split gate field effect transistor (FET) device | Chrong-Jung Lin, Sheng-Wei Tsao, Di-Son Kuo, Jack Y. Yeh, Chung-Li Chang +1 more | 2002-10-15 |
| 6420233 | Split gate field effect transistor (FET) device employing non-linear polysilicon floating gate electrode dopant profile | Chia-Ta Hsieh, Di-Son Kuo, Jake Yeh, Chung-Li Chang, Chrong-Jung Lin | 2002-07-16 |
| 6417046 | Modified nitride spacer for solving charge retention issue in floating gate memory cell | Ming-Chou Ho, Chang-Song Lin, Chuan-Li Chang, Hsin-Ming Chen, Di-Son Kuo | 2002-07-09 |
| 6403494 | Method of forming a floating gate self-aligned to STI on EEPROM | Di-Son Kuo, Jack Y. Yeh, Chia-Ta Hsieh, Chuan-Li Chang | 2002-06-11 |
| 6387757 | Sacrificial self aligned spacer layer ion implant mask method for forming a split gate field effect transistor (FET) device | Di-Son Kuo, Jake Yeh, Chia-Da Hsieh, Chuan-Li Chang, Sheng-Wei Tsaur | 2002-05-14 |
| 6348382 | Integration process to increase high voltage breakdown performance | Hung-Der Su, Chrong-Jung Lin, Jong Chen | 2002-02-19 |