Issued Patents All Time
Showing 226–244 of 244 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6333228 | Method to improve the control of bird's beak profile of poly in split gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Jack Y. Yeh, Di-Son Kuo | 2001-12-25 |
| 6331721 | Memory cell with built in erasure feature | Kuo-Tung Sung, Huoy-Jong Wu | 2001-12-18 |
| 6312989 | Structure with protruding source in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo | 2001-11-06 |
| 6309928 | Split-gate flash cell | Hung-Cheng Sung, Di-Son Kuo, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin | 2001-10-30 |
| 6297099 | Method to free control tunneling oxide thickness on poly tip of flash | Chia-Ta Hsieh, Di-Son Kuo, Jack Y. Yeh, Chrong-Jung Lin, Chung-Li Chang | 2001-10-02 |
| 6297098 | Tilt-angle ion implant to improve junction breakdown in flash memory application | Chrong-Jung Lin, Hung-Der Su, Jong Chen | 2001-10-02 |
| 6261905 | Flash memory structure with stacking gate formed using damascene-like structure | Jong Chen, Chrong-Jong Lin, Hung-Der Su | 2001-07-17 |
| 6251744 | Implant method to improve characteristics of high voltage isolation and high voltage breakdown | Hung-Der Su, Chrong-Jung Lin, Jong Chen, Hung-Cheng Sung, Di-Son Kuo | 2001-06-26 |
| 6245657 | Self-aligned, low contact resistance, via fabrication process | Hsin-Ming Chen | 2001-06-12 |
| 6204126 | Method to fabricate a new structure with multi-self-aligned for split-gate flash | Chia-Ta Hsieh, Tai-Fen Lin, Chuang-Ke Yeh, Hung-Cheng Sung, Di-Son Kuo | 2001-03-20 |
| 6130168 | Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process | Di-Son Kuo, Chrong-Jung Lin, Hung-Der Su, Jong Chen | 2000-10-10 |
| 6127229 | Process of forming an EEPROM device having a split gate | Di-Son Kuo, Hung-Cheng Sung, Jack Y. Yeh, Chia-Ta Hsieh, Yai-Fen Lin | 2000-10-03 |
| 6124177 | Method for making deep sub-micron mosfet structures having improved electrical characteristics | Chrong-Jung Lin, Hung-Der Su, Jong Chen | 2000-09-26 |
| 6117732 | Use of a metal contact structure to increase control gate coupling capacitance for a single polysilicon non-volatile memory cell | Chuan-Li Chang, Ming-Chou Ho, Chang-Song Lin, Di-Son Kuo | 2000-09-12 |
| 6110780 | Using NO or N.sub.2 O treatment to generate different oxide thicknesses in one oxidation step for single poly non-volatile memory | Mo Yu, Syun-Min Jang | 2000-08-29 |
| 6110782 | Method to combine high voltage device and salicide process | Chuan-Li Chang, Ming-Chon Ho, Chang-Song Lin, Di-Son Kwo | 2000-08-29 |
| 6063548 | Method for making DRAM using a single photoresist masking step for making capacitors with node contacts | Chung-Cheng Wu | 2000-05-16 |
| 6001687 | Process for forming self-aligned source in flash cell using SiN spacer as hard mask | Di-Son Kuo, Chrong-Jung Lin, Hung-Der Su, Jong Chen | 1999-12-14 |
| 5963806 | Method of forming memory cell with built-in erasure feature | Kuo-Tung Sung, Huoy-Jong Wu | 1999-10-05 |