Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12249564 | Package structure, RDL structure comprising redistribution layer having ground plates and signal lines | Chien-Hsun Chen, Jiun Yi Wu | 2025-03-11 |
| 12183682 | Semiconductor package and manufacturing method thereof | Chien-Hsun Chen, Chien-Hsun Lee, Chung-Shi Liu, Jiun Yi Wu, Tsung-Ding Wang | 2024-12-31 |
| 11961814 | Integrated circuit package and method | Chien-Hsun Chen, Jiun Yi Wu, Chung-Shi Liu, Chen-Hua Yu | 2024-04-16 |
| 11670575 | Package structure, RDL structure comprising redistribution layer having ground plates and signal lines | Chien-Hsun Chen, Jiun Yi Wu | 2023-06-06 |
| 11239193 | Integrated circuit package and method | Chien-Hsun Chen, Jiun Yi Wu, Chung-Shi Liu, Chen-Hua Yu | 2022-02-01 |
| 11177218 | Package including metallic bolstering pattern and manufacturing method of the package | Jiun Yi Wu, Chien-Hsun Lee, Chien-Hsun Chen | 2021-11-16 |
| 11171090 | Semiconductor device and method of manufacture | Jiun Yi Wu, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Chien-Hsun Chen | 2021-11-09 |
| 11088059 | Package structure, RDL structure comprising redistribution layer having ground plates and signal lines and method of forming the same | Chien-Hsun Chen, Jiun Yi Wu | 2021-08-10 |
| 10879201 | Semiconductor package for wafer level packaging and manufacturing method thereof | Ming-Yen Chiu, Tsung-Shu Lin | 2020-12-29 |
| 10756038 | Semiconductor package and manufacturing method thereof | Ming-Yen Chiu, Tsung-Shu Lin | 2020-08-25 |
| 9812416 | Semiconductor arrangement and formation thereof | Jiun Yi Wu, Hsueh-Lung Cheng | 2017-11-07 |
| 9646928 | Semiconductor arrangement and formation thereof | Jiun Yi Wu, Hsueh-Lung Cheng | 2017-05-09 |
| 8976529 | Lid design for reliability enhancement in flip chip package | Wen-Yi Lin, Po-Yao Lin, Tsung-Shu Lin, Kuo-Chin Chang | 2015-03-10 |