Issued Patents All Time
Showing 76–100 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10741539 | Standard cells and variations thereof within a standard cell library | Jerry Chang Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong WANG +2 more | 2020-08-11 |
| 10733352 | Integrated circuit and layout method for standard cell structures | Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien | 2020-08-04 |
| 10678987 | Cell layout method and system for creating stacked 3D integrated circuit having two tiers | Fong-Yuan Chang | 2020-06-09 |
| 10664565 | Method and system of expanding set of standard cells which comprise a library | Chi-Lin Liu, Jerry Chang Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2020-05-26 |
| 10559558 | Pin modification for standard cells | Fong-Yuan Chang, Ting-Wei Chiang, Chung-Te Lin, Jung-Chan Yang, Lee-Chung Lu +2 more | 2020-02-11 |
| 10552568 | Method of modifying cell and global connection routing method | Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang | 2020-02-04 |
| 10521545 | Placement constraint method for multiple patterning of cell-based chip design | Shao-Huan Wang, Fong-Yuan Chang, Po-Hsiang Huang | 2019-12-31 |
| 10515944 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen +3 more | 2019-12-24 |
| 10509887 | Must-join pin sign-off method | Ming-Huei Tsai, Shao-Huan Wang, Shu-Yu Chen, Wen-Hao Chen, Chun-Chen Chen | 2019-12-17 |
| 10402534 | Integrated circuit layout methods, structures, and systems | Po-Hsiang Huang, Fong-Yuan Chang | 2019-09-03 |
| 10396063 | Circuit with combined cells and method for manufacturing the same | Fong-Yuan Chang, Lee-Chung Lu, Yi-Kan Cheng, Po-Hsiang Huang, Shun Li Chen +4 more | 2019-08-27 |
| 10312192 | Integrated circuit having staggered conductive features | Fong-Yuan Chang, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen | 2019-06-04 |
| 10289794 | Layout for semiconductor device including via pillar structure | Shao-Huan Wang, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou | 2019-05-14 |
| 10262981 | Integrated circuit, system for and method of forming an integrated circuit | Fong-Yuan Chang, Jyun-Hao Chang, Po-Hsiang Huang, Lipen Yuan | 2019-04-16 |
| 10192019 | Separation and minimum wire length constrained maze routing method and system | Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak | 2019-01-29 |
| 10157840 | Integrated circuit having a high cell density | Chung-Hsing Wang, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2018-12-18 |
| 10157251 | Method and system for partitioning circuit cells | Hung-Chih Ou, Chun-Chen Chen | 2018-12-18 |
| 10128234 | Electromigration resistant semiconductor device | Ni-Wan Fan, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Chi-Yu Lu | 2018-11-13 |
| 9996657 | Systems and methods for generating a multiple patterning lithography compliant integrated circuit layout | Chun-Chen Chen, Fong-Yuan Chang, Shao-Huan Wang | 2018-06-12 |
| 9846759 | Global connection routing method and system for performing the same | Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang | 2017-12-19 |
| 9665679 | Systems and methods for designing integrated circuits with consideration of horizontal and vertical wiring demand ratios | Fong-Yuan Chang, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak | 2017-05-30 |
| 9003350 | Multiple level spine routing | Fong-Yuan Chang, Wei-Shun Chuang, Hsian-Ho Chang, Ruey-Shi Rau | 2015-04-07 |
| 8959473 | Multiple level spine routing | Fong-Yuan Chang, Wei-Shun Chuang, Hsian-Ho Chang, Ruey-Shi Rau | 2015-02-17 |
| 8875081 | Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio | Fong-Yuan Chang, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak | 2014-10-28 |
| 8832632 | Compact routing | Fong-Yuan Chang | 2014-09-09 |