Issued Patents All Time
Showing 51–75 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11275886 | Integrated circuit and method of forming same and a system | Wen-Hao Chen, Chun-Yao Ku, Shao-Huan Wang, Hung-Chih Ou | 2022-03-15 |
| 11182533 | Standard cells and variations thereof within a standard cell library | Jerry Chang Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong WANG +2 more | 2021-11-23 |
| 11170152 | Integrated circuit and layout method for standard cell structures | Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien | 2021-11-09 |
| 11170149 | Placement constraint method for multiple patterning of cell-based chip design | Shao-Huan Wang, Fong-Yuan Chang, Po-Hsiang Huang | 2021-11-09 |
| 11138362 | Integrated circuit layout method and system | Po-Hsiang Huang, Fong-Yuan Chang | 2021-10-05 |
| 11138360 | Semiconductor device with filler cell region, method of generating layout diagram and system for same | Po-Hsiang Huang, Chin-Chou Liu, Fong-Yuan Chang, Hui-Zhong Zhuang, Meng Wang +2 more | 2021-10-05 |
| 11132488 | Method of modifying cell, system for modifying cell and global connection routing method | Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang | 2021-09-28 |
| 11080453 | Integrated circuit fin layout method, system, and structure | Po-Hsiang Huang, Chih-Hsin Ko, Fong-Yuan Chang, Clement Hsingjen Wann, Li-Chun Tien +1 more | 2021-08-03 |
| 11062076 | Method and system of generating a layout diagram | Meng-Kai Hsu, Wai-Kei Mak, Ting-Chi Wang, Yu-Hsiang Cheng, Ding-Wei Huang | 2021-07-13 |
| 11037920 | Pin modification for standard cells | Fong-Yuan Chang, Ting-Wei Chiang, Chung-Te Lin, Jung-Chan Yang, Lee-Chung Lu +2 more | 2021-06-15 |
| 11030366 | Method and system of expanding set of standard cells which comprise a library | Chi-Lin Liu, Jerry Chang Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2021-06-08 |
| 11030372 | Method for generating layout diagram including cell having pin patterns and semiconductor device based on same | Pin-Dai Sue, Chin-Chou Liu, Fong-Yuan Chang, Lee-Chung Lu, Yen-Hung Lin +4 more | 2021-06-08 |
| 10990745 | Integrated circuit and method of forming same and a system | Shao-Huan Wang, Wen-Hao Chen, Chun-Yao Ku, Hung-Chih Ou | 2021-04-27 |
| 10977418 | Semiconductor device with cell region, method of generating layout diagram and system for same | Fong-Yuan Chang, Ho Che Yu | 2021-04-13 |
| 10970450 | Cell structures and semiconductor devices having same | Fong-Yuan Chang, Jyun-Hao Chang, Ho Che Yu, Lee-Chung Lu, Ni-Wan Fan +3 more | 2021-04-06 |
| 10964685 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen +3 more | 2021-03-30 |
| 10903239 | Integrated circuit device with improved layout | Fong-Yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin +2 more | 2021-01-26 |
| 10878165 | Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same | Fong-Yuan Chang, Chin-Chou Liu, Po-Hsiang Huang | 2020-12-29 |
| 10868538 | Logic cell structure and integrated circuit with the logic cell structure | Shao-Huan Wang, Chun-Chen Chen, Kuo-Nan Yang | 2020-12-15 |
| 10817643 | Method of designing semiconductor device and system for implementing the method | Shao-Huan Wang, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou | 2020-10-27 |
| 10804200 | Integrated circuit having a high cell density | Chung-Hsing Wang, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2020-10-13 |
| 10797041 | Integrated circuit, system for and method of forming an integrated circuit | Fong-Yuan Chang, Jyun-Hao Chang, Po-Hsiang Huang, Lipen Yuan | 2020-10-06 |
| 10776551 | Method and system of revising a layout diagram | Meng-Kai Hsu, Wai-Kei Mak, Ting-Chi Wang, Yu-Hsiang Cheng, Ding-Wei Huang | 2020-09-15 |
| 10776557 | Integrated circuit structure | Po-Hsiang Huang, Fong-Yuan Chang | 2020-09-15 |
| 10777505 | Method of fabricating integrated circuit having staggered conductive features | Fong-Yuan Chang, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen | 2020-09-15 |