Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11239228 | Integrated circuit layout and method of configuring the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2022-02-01 |
| 11216608 | Reduced area standard cell abutment configurations | Chi-Yu Lu, Hui-Zhong Zhuang, Li-Chun Tien, Yi-Hsin Ko | 2022-01-04 |
| 11088067 | Semiconductor device and layout design thereof | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2021-08-10 |
| 11030372 | Method for generating layout diagram including cell having pin patterns and semiconductor device based on same | Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu, Yen-Hung Lin +4 more | 2021-06-08 |
| 10950594 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2021-03-16 |
| 10868008 | Double rule integrated circuit layouts for a dual transmission gate | Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Wei-Cheng Lin | 2020-12-15 |
| 10867104 | Isolation circuit between power domains | Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Jerry Chang Jui Kao, Yu-Ti Su +2 more | 2020-12-15 |
| 10867113 | Transmission gate structure, layout, methods, and system | Shao-Lun Chien, Ting-Wei Chiang, Li-Chun Tien, Ting Yu Chen | 2020-12-15 |
| 10867986 | Semiconductor device having fin structure | Shun Li Chen, Chung-Te Lin, Hui-Zhong Zhuang, Jung-Chan Yang | 2020-12-15 |
| 10861790 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng +6 more | 2020-12-08 |
| 10727177 | Semiconductor device and layout design thereof | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2020-07-28 |
| 10707199 | Integrated circuit layout and method of configuring the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2020-07-07 |
| 10522542 | Double rule integrated circuit layouts for a dual transmission gate | Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Wei-Cheng Lin | 2019-12-31 |
| 10325900 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2019-06-18 |
| 10277227 | Semiconductor device layout | Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Shun Li Chen | 2019-04-30 |
| 10269784 | Integrated circuit layout and method of configuring the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2019-04-23 |
| 10170422 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng +6 more | 2019-01-01 |
| 10163880 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2018-12-25 |
| 10141256 | Semiconductor device and layout design thereof | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2018-11-27 |
| 9911697 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng +6 more | 2018-03-06 |
| 9563731 | Cell boundaries for self aligned multiple patterning abutments | Chin-Hsiung Hsu, Li-Chun Tien, Ching-Hsiang Chang, Wen-Hao Chen, Cheng-I Huang | 2017-02-07 |
| 9478540 | Adaptive fin design for FinFETs | Tsong-Hua Ou, Shu-Min Chen, Li-Chun Tien, Ru-Gun Liu | 2016-10-25 |
| 9478609 | Integrated circuit with multiple cells having different heights | Ting-Wei Chiang, Li-Chun Tien, Ming Jin Huang | 2016-10-25 |
| 9202696 | Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits | Jen-Hang Yang, Chun-Fu Chen, Hui-Zhong Zhuang | 2015-12-01 |
| 8872269 | Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits | Jen-Hang Yang, Chun-Fu Chen, Hui-Zhong Zhuang | 2014-10-28 |