Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11437371 | Field effect transistors with negative capacitance layers | Chansyun David Yang, Chan-Lon Yang | 2022-09-06 |
| 11367695 | Interposer with capacitors | Fong-Yuan Chang, Cheng-Hung Yeh, Hsiang-Ho Chang, Po-Hsiang Huang, Chin-Her Chien +4 more | 2022-06-21 |
| 11335606 | Power rails for stacked semiconductor device | Chansyun David Yang, Chan-Lon Yang | 2022-05-17 |
| 11282711 | Plasma-assisted etching of metal oxides | Chansyun David Yang, Chan-Lon Yang | 2022-03-22 |
| 11276604 | Radical-activated etching of metal oxides | Chansyun David Yang, Chan-Lon Yang, Perng-Fei Yuh | 2022-03-15 |
| 11150559 | Laser interference fringe control for higher EUV light source and EUV throughput | Chansyun David Yang, Chan-Lon Yang | 2021-10-19 |
| 11114547 | Field effect transistor with negative capacitance dieletric structures | Chansyun David Yang, Chan-Lon Yang | 2021-09-07 |
| 8115500 | Accurate capacitance measurement for ultra large scale integrated circuits | Yih-Yuh Doong, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang | 2012-02-14 |
| 7880494 | Accurate capacitance measurement for ultra large scale integrated circuits | Yih-Yuh Doong, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang | 2011-02-01 |
| 7772868 | Accurate capacitance measurement for ultra large scale integrated circuits | Yih-Yuh Doong, Yuh-Jier Mii, Sally Liu, Lien Jung Hung, Victor Chih Yuan Chang | 2010-08-10 |
| 6643831 | Method and system for extraction of parasitic interconnect impedance including inductance | Li-Fu Chang, Robert G. Mathews, Martin G. Walker | 2003-11-04 |
| 6403389 | Method for determining on-chip sheet resistivity | Robert G. Mathews, Shih-tsun Alexander Chou, Abhay Dubey | 2002-06-11 |
| 6381730 | Method and system for extraction of parasitic interconnect impedance including inductance | Li-Fu Chang, Robert G. Mathews, Martin G. Walker | 2002-04-30 |
| 6312963 | Methods for determining on-chip interconnect process parameters | Shih-tsun Alexander Chou, Robert G. Mathews | 2001-11-06 |
| 6311312 | Method for modeling a conductive semiconductor substrate | Robert G. Mathews, Li-Fu Chang, Xu Yang | 2001-10-30 |
| 6291254 | Methods for determining on-chip interconnect process parameters | Shih-tsun Alexander Chou, Robert G. Mathews | 2001-09-18 |
| 6057171 | Methods for determining on-chip interconnect process parameters | Shih-tsun Alexander Chou, Robert G. Mathews | 2000-05-02 |
| 5901063 | System and method for extracting parasitic impedance from an integrated circuit layout | Douglas Francis Kaufman, Martin G. Walker | 1999-05-04 |
| 5610833 | Computer-aided design methods and apparatus for multilevel interconnect technologies | Norman Chang, Keunmyung Lee, Soo Young Oh | 1997-03-11 |