Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7222311 | Method and apparatus for interconnect-driven optimization of integrated circuit design | Douglas Francis Kaufman, Hazem Almusa, Vinay Srinivas, Donald V. Organ, Larry Ke +2 more | 2007-05-22 |
| 6643831 | Method and system for extraction of parasitic interconnect impedance including inductance | Keh-Jeng Chang, Li-Fu Chang, Martin G. Walker | 2003-11-04 |
| 6591407 | Method and apparatus for interconnect-driven optimization of integrated circuit design | Douglas Francis Kaufman, Hazem Almusa, Vinay Srinivas, Donald V. Organ, Larry Ke +2 more | 2003-07-08 |
| 6403389 | Method for determining on-chip sheet resistivity | Keh-Jeng Chang, Shih-tsun Alexander Chou, Abhay Dubey | 2002-06-11 |
| 6381730 | Method and system for extraction of parasitic interconnect impedance including inductance | Keh-Jeng Chang, Li-Fu Chang, Martin G. Walker | 2002-04-30 |
| 6312963 | Methods for determining on-chip interconnect process parameters | Shih-tsun Alexander Chou, Keh-Jeng Chang | 2001-11-06 |
| 6311312 | Method for modeling a conductive semiconductor substrate | Keh-Jeng Chang, Li-Fu Chang, Xu Yang | 2001-10-30 |
| 6291254 | Methods for determining on-chip interconnect process parameters | Shih-tsun Alexander Chou, Keh-Jeng Chang | 2001-09-18 |
| 6057171 | Methods for determining on-chip interconnect process parameters | Shih-tsun Alexander Chou, Keh-Jeng Chang | 2000-05-02 |