Issued Patents All Time
Showing 101–125 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6426855 | ESD protection circuit for different power supplies | Jiaw-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu | 2002-07-30 |
| 6420221 | Method of manufacturing a highly latchup-immune CMOS I/O structure | Jiaw-Ren Shih, Shui-Hung Chen, Ping Lung Liao | 2002-07-16 |
| 6414532 | Gate ground circuit approach for I/O ESD protection | Hung-Der Su, Yi-Hsun Wu, Mau-Lin Wu | 2002-07-02 |
| 6400542 | ESD protection circuit for different power supplies | Jian-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu | 2002-06-04 |
| 6362035 | Channel stop ion implantation method for CMOS integrated circuits | Jiaw-Ren Shih, Shui-Hung Chen, Hsien-Chin Lin | 2002-03-26 |
| 6358781 | Uniform current distribution SCR device for high voltage ESD protection | Kuo-Chio Liu, Bing-Lung Liao, Jiaw-Ren Shih | 2002-03-19 |
| 6323074 | High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain | Jyh-Min Jiang, Kuo-Chio Liu, Ruey-Hsin Liu | 2001-11-27 |
| 6323523 | N-type structure for n-type pull-up and down I/O protection circuit | Yi-Hsun Wu, Shui-Hung Chen, Jiaw-Ren Shih | 2001-11-27 |
| 6306695 | Modified source side inserted anti-type diffusion ESD protection device | Jiaw-Ren Shih, Shui-Hung Chen, Yi-Hsun Wu | 2001-10-23 |
| 6303454 | Process for a snap-back flash EEPROM cell | Juang-Ker Yeh, Kuo-Reay Peng, Ming-Chou Ho | 2001-10-16 |
| 6277723 | Plasma damage protection cell using floating N/P/N and P/N/P structure | Jiaw-Ren Shih, Shui-Hung Chen, Chrong-Jung Lin | 2001-08-21 |
| 6271999 | ESD protection circuit for different power supplies | Jiaw-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu | 2001-08-07 |
| 6268992 | Displacement current trigger SCR | Jiaw-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu | 2001-07-31 |
| 6258672 | Method of fabricating an ESD protection device | Jiaw-Ren Shih, Huey-Liang Hwang | 2001-07-10 |
| 6249414 | Displacement current trigger SCR | Jiaw-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu | 2001-06-19 |
| 6246075 | Test structures for monitoring gate oxide defect densities and the plasma antenna effect | Hung-Der Su, Di-Son Kuo | 2001-06-12 |
| 6232160 | Method of delta-channel in deep sub-micron process | Jiaw-Ren Shih, Shui-Hung Chen | 2001-05-15 |
| 6214670 | Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance | Jiaw-Ren Shih, Shui-Hung Chen | 2001-04-10 |
| 6207482 | Integration method for deep sub-micron dual gate transistor design | Jiaw-Ren Shih, Shui-Hung Chen, Chia-Hung Tunga | 2001-03-27 |
| 6190954 | Robust latchup-immune CMOS structure | Shui-Hung Chen, Jiaw-Ren Shih | 2001-02-20 |
| 6171891 | Method of manufacture of CMOS device using additional implant regions to enhance ESD performance | Yi-Hsun Wu, Tiaw-Ren Shih | 2001-01-09 |
| 6122201 | Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM | Kuo-Reay Peng, Shui-Hung Chen, Jiaw-Ren Shih | 2000-09-19 |
| 6097066 | Electro-static discharge protection structure for semiconductor devices | Yi-Hsun Wu, Jiaw-Ren Shih | 2000-08-01 |
| 6066879 | Combined NMOS and SCR ESD protection device | Kuo-Chio Liu | 2000-05-23 |
| 6055183 | Erase method of flash EEPROM by using snapback characteristic | Ming-Chou Ho, Kuo-Reay Peng, Juang-Ke Yeh | 2000-04-25 |