Issued Patents All Time
Showing 126–148 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6049484 | Erase method to improve flash EEPROM endurance by combining high voltage source erase and negative gate erase | Kuo-Reay Peng, Juang-Ke Yeh, Ming-Chou Ho | 2000-04-11 |
| 6049486 | Triple mode erase scheme for improving flash EEPROM cell threshold voltage (V.sub.T) cycling closure effect | Kuo-Reay Peng | 2000-04-11 |
| 6028324 | Test structures for monitoring gate oxide defect densities and the plasma antenna effect | Hung-Der Su, Di-Son Kuo | 2000-02-22 |
| 6025628 | High breakdown voltage twin well device with source/drain regions widely spaced from fox regions | Kuo-Reay Peng, Jung-Ke Yeh, Hsiu-Han Liao | 2000-02-15 |
| 6008974 | Electrostatic discharge protective circuit for reducing an undesired channel turn-on | Yi-Hsun Wu, Jiaw-Ren Shih, Jing-Meng Liu | 1999-12-28 |
| 5949717 | Method to improve flash EEPROM cell write/erase threshold voltage closure | Ming-Chou Ho, Juang-Ker Yeh, Kuo-Reay Peng | 1999-09-07 |
| 5939756 | Added P-well implantation for uniform current distribution in ESD protection device | — | 1999-08-17 |
| 5933732 | Nonvolatile devices with P-channel EEPROM devices as injector | Yai-Fen Lin, Shiou-Hann Liaw, Di-Son Kuo | 1999-08-03 |
| 5913122 | Method of making high breakdown voltage twin well device with source/drain regions widely spaced from FOX regions | Kuo-Reay Peng, Jung-Ke Yeh, Hsiu-Han Liao | 1999-06-15 |
| 5903499 | Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate erase | Kuo-Reay Peng, Juang-Ke Yeh, Ming-Chou Ho | 1999-05-11 |
| 5898205 | Enhanced ESD protection circuitry | — | 1999-04-27 |
| 5891792 | ESD device protection structure and process with high tilt angle GE implant | Jiaw-Ren Shih | 1999-04-06 |
| 5872379 | Low voltage turn-on SCR for ESD protection | — | 1999-02-16 |
| 5862078 | Mixed mode erase method to improve flash eeprom write/erase threshold closure | Juang-Ker Yeh, Kuo-Reay Peng, Ming-Chou Ho | 1999-01-19 |
| 5838618 | Bi-modal erase method for eliminating cycling-induced flash EEPROM cell write/erase threshold closure | Juang-Ker Yeh, Kuo-Reay Peng, Ming-Chou Ho | 1998-11-17 |
| 5828605 | Snapback reduces the electron and hole trapping in the tunneling oxide of flash EEPROM | Kuo-Reay Peng, Juang-Ke Yeh, Ming-Chon Ho | 1998-10-27 |
| 5811856 | Layout of ESD input-protection circuit | — | 1998-09-22 |
| 5726933 | Clipped sine shaped waveform to reduce the cycling-induced electron trapping in the tunneling oxide of flash EEPROM | Kuo-Reay Peng, Juang-Ke Yeh, Ming-Chou Ho | 1998-03-10 |
| 5663082 | Electrostactic discharge protection structure for lightly doped CMOS integrated circuit process | — | 1997-09-02 |
| 5659245 | ESD bypass and EMI shielding trace design in burn-in board | King-Ho Ping | 1997-08-19 |
| 5565790 | ESD protection circuit with field transistor clamp and resistor in the gate circuit of a clamp triggering FET | — | 1996-10-15 |
| 5563525 | ESD protection device with FET circuit | — | 1996-10-08 |
| 5561387 | Method for measuring gate insulation layer thickness | — | 1996-10-01 |