Issued Patents All Time
Showing 51–75 of 153 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11798989 | Strained nanowire CMOS device and method of forming | Cheng-Yi Peng, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu | 2023-10-24 |
| 11757045 | Semiconductor device and method of manufacturing the same | Chao-Ching Cheng, Chun-Chieh Lu, Tzu-Chiang Chen | 2023-09-12 |
| 11749718 | Semiconductor device and manufacturing method thereof | Yi-Tse Hung, Ang-Sheng Chou, Tzu-Chiang Chen, Chao-Ching Cheng | 2023-09-05 |
| 11742352 | Vertical semiconductor device with steep subthreshold slope | Szu-Wei Huang, Chih Chieh Yeh, Yee-Chia Yeo | 2023-08-29 |
| 11735259 | Read method, write method and memory circuit using the same | Carlos H. Diaz, Tzu-Chiang Chen, Yih Wang | 2023-08-22 |
| 11721376 | Memory device, operation method of memory device and operation method of memory circuit | Chung-Te Lin, Shy-Jay Lin, Tzu-Chiang Chen, Ming-Yuan Song, Hon-Sum Philip Wong | 2023-08-08 |
| 11715798 | FeFET of 3D structure for capacitance matching | Chih-Sheng Chang, Tzu-Chiang Chen | 2023-08-01 |
| 11652141 | Strained nanowire CMOS device and method of forming | Cheng-Yi Peng, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu | 2023-05-16 |
| 11626328 | Strain enhancement for FinFETs | Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Wei-Jen Lai | 2023-04-11 |
| 11605779 | Memory cell, method of forming the same, and semiconductor die | Jer-Fu Wang, Jung-Piao Chiu, Yu-Sheng Chen, Tzu-Chiang Chen | 2023-03-14 |
| 11600720 | Forming semiconductor structures with two-dimensional materials | Chao-Ching Cheng, Chun-Chieh Lu, Ming-Yang Li, Tzu-Chiang Chen | 2023-03-07 |
| 11581426 | Semiconductor device and manufacturing method thereof | Chao-Ching Cheng, Tzu-Chiang Chen, I-Sheng Chen | 2023-02-14 |
| 11569236 | Replacement gate process for FinFET | Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen | 2023-01-31 |
| 11515305 | Structure and formation method of hybrid semiconductor device | I-Sheng Chen, Tzu-Chiang Chen | 2022-11-29 |
| 11482571 | Memory array with asymmetric bit-line architecture | Chao-Ching Cheng, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen | 2022-10-25 |
| 11476356 | Fin field-effect transistor device with low-dimensional material and method | Yi-Tse Hung, Chao-Ching Cheng, Tse-An Chen, Tzu-Chiang Chen, Lain-Jong Li | 2022-10-18 |
| 11437468 | Isolation structures of semiconductor devices | Chao-Ching Cheng, Tzu-Chiang Chen, I-Sheng Chen | 2022-09-06 |
| 11417729 | Transistors with channels formed of low-dimensional materials and method forming same | Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Tzu-Chiang Chen, Lain-Jong Li | 2022-08-16 |
| 11398476 | Structure and formation method of semiconductor device with hybrid fins | Jin-Aun Ng, Kuo-Cheng Chiang, Tzu-Chiang Chen, I-Sheng Chen | 2022-07-26 |
| 11393926 | Multi-gate device | Huan-Sheng Wei, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu +1 more | 2022-07-19 |
| 11393925 | Semiconductor device structure with nanostructure | Yu-Chao Lin, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee | 2022-07-19 |
| 11380369 | Semiconductor device including memory cells and method for manufacturing thereof | Yu-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen | 2022-07-05 |
| 11367482 | Read method, write method and memory circuit using the same | Carlos H. Diaz, Tzu-Chiang Chen, Yih Wang | 2022-06-21 |
| 11349069 | Resistive memory devices using a carbon-based conductor line and methods for forming the same | Chao-Ching Cheng, Tzu-Chiang Chen, Lain-Jong Li | 2022-05-31 |
| 11348920 | Vertical semiconductor device with steep subthreshold slope | Szu-Wei Huang, Chih Chieh Yeh, Yee-Chia Yeo | 2022-05-31 |