Issued Patents All Time
Showing 101–125 of 282 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9929272 | Fin structure of FinFET | Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun | 2018-03-27 |
| 9929158 | Systems and methods for integrating different channel materials into a CMOS circuit by using a semiconductor structure having multiple transistor layers | Yi-Tang Lin | 2018-03-27 |
| 9929133 | Semiconductor logic circuits fabricated using multi-layer structures | Yi-Tang Lin | 2018-03-27 |
| 9922827 | Method of forming a semiconductor structure | Liang-Gi Yao, Chia-Cheng Chen, Ta-Ming Kuan, Jeff J. Xu | 2018-03-20 |
| 9899496 | Method of making a finFET device | Sey-Ping Sun, Sung-Li Wang, Chin-Hsiang Lin, Neng-Kuo Chen | 2018-02-20 |
| 9893160 | Methods of forming gate dielectric material | Liang-Gi Yao, Chia-Cheng Chen | 2018-02-13 |
| 9887290 | Silicon germanium source/drain regions | Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko | 2018-02-06 |
| 9887274 | FinFETs and methods for forming the same | Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi Kang Liu, Yung-Ta Li +2 more | 2018-02-06 |
| 9870956 | FinFETs with nitride liners and methods of forming the same | Neng-Kuo Chen, Gin-Chen Huang, Ching-Hong Jiang, Sey-Ping Sun | 2018-01-16 |
| 9870920 | Growing III-V compound semiconductors from trenches filled with intermediate layers | Chih-Hsin Ko, Cheng-Hsien Wu | 2018-01-16 |
| 9859380 | FinFETs with strained well regions | Yi-Jing Lee, Chi-Wen Liu, Cheng-Hsien Wu, Chih-Hsin Ko | 2018-01-02 |
| 9831322 | Channel epitaxial regrowth flow (CRF) | Ching-Feng Fu, Shih-Ting Hung, Hsin-Chih Chen, Chih-Hsin Ko | 2017-11-28 |
| 9812551 | Method of forming the gate electrode of field effect transistor | Neng-Kuo Chen, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun | 2017-11-07 |
| 9786543 | Isolation structure of semiconductor device | Shu-Han Chen, Cheng-Hsien Wu, Chih-Hsin Ko | 2017-10-10 |
| 9780216 | Combination FinFET and methods of forming same | Yu-Lien Huang, Tsu-Hsiu Perng, Tung Ying Lee, Ming-Huan Tsai | 2017-10-03 |
| 9780174 | Methods for forming semiconductor regions in trenches | Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko | 2017-10-03 |
| 9773809 | Systems and methods for a semiconductor structure having multiple semiconductor-device layers | Yi-Tang Lin, Chun Hsiung Tsai | 2017-09-26 |
| 9773889 | Method of semiconductor arrangement formation | Wei-Chieh Chen, Hao-Hsiung Lin, Shu-Han Chen, You-Ru Lin, Cheng-Hsien Wu +1 more | 2017-09-26 |
| 9768305 | Gradient ternary or quaternary multiple-gate transistor | Chih-Hsin Ko | 2017-09-19 |
| 9748143 | FinFETs with strained well regions | Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko | 2017-08-29 |
| 9748388 | Method of forming strained structures of semiconductor devices | Cheng-Hsien Wu, Chih-Hsin Ko | 2017-08-29 |
| 9698060 | Germanium FinFETs with metal gates and stressors | Chih Chieh Yeh, Chih-Sheng Chang | 2017-07-04 |
| 9673292 | Semiconductor device having modified profile metal gate | Yu-Lien Huang, Chi-Wen Liu, Ming-Huan Tsai, Zhao-Cheng Chen | 2017-06-06 |
| 9646872 | Systems and methods for a semiconductor structure having multiple semiconductor-device layers | Yi-Tang Lin, Chun Hsiung Tsai | 2017-05-09 |
| 9634001 | System and methods for converting planar design to FinFET design | Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh, Ting-Chu Ko, Chung-Hsien Chen | 2017-04-25 |