Issued Patents All Time
Showing 326–350 of 937 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11855205 | Semiconductor device with negative capacitance structure | Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui | 2023-12-26 |
| 11855216 | Inner spacers for gate-all-around transistors | Kuo-Cheng Chiang, Zhi-Chang Lin, Shih-Cheng Chen, Pei-Hsun Wang, Lo-Heng Chang +1 more | 2023-12-26 |
| 11848372 | Method and structure for reducing source/drain contact resistance at wafer backside | Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Kuan-Lun Cheng | 2023-12-19 |
| 11848368 | Transistors with different threshold voltages | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang | 2023-12-19 |
| 11848326 | Integrated circuits with gate cut features | Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Kuo-Cheng Ching | 2023-12-19 |
| 11848329 | Semiconductor structure with self-aligned backside power rail | Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng | 2023-12-19 |
| 11842965 | Backside power rail structure and methods of forming same | Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan | 2023-12-12 |
| 11837504 | Self-aligned structure for semiconductor devices | Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Kuan-Ting Pan | 2023-12-05 |
| 11837506 | FinFET devices and methods of forming the same | Jui-Chien Huang, Kuo-Cheng Ching, Chun-Hsiung Lin, Pei-Hsun Wang | 2023-12-05 |
| 11830769 | Semiconductor device with air gaps and method of fabrication thereof | Chia-Hao Chang, Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng | 2023-11-28 |
| 11830924 | Nanosheet device with dipole dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu | 2023-11-28 |
| 11824101 | High aspect ratio gate structure formation | Sai-Hooi Yeong, Chi On Chui, Kai-Hsuan Lee, Kuan-Lun Cheng | 2023-11-21 |
| 11824058 | Method of forming semiconductor device | Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng | 2023-11-21 |
| 11817491 | Semiconductor device having an air gap along a gate spacer | Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin | 2023-11-14 |
| 11817504 | Isolation structures and methods of forming the same in field-effect transistors | Shi Ning Ju, Kuo-Cheng Chiang, Guan-Lin Chen, Kuan-Lun Cheng | 2023-11-14 |
| 11804486 | Backside power rail and methods of forming the same | Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang +1 more | 2023-10-31 |
| 11804489 | Semiconductor device and manufacturing method thereof | Kuo-Cheng Ching, Chih-Liang Chen, Shi Ning Ju | 2023-10-31 |
| 11798944 | Integration of silicon channel nanostructures and silicon-germanium channel nanostructures | Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng, Guan-Lin Chen | 2023-10-24 |
| 11799019 | Gate isolation feature and manufacturing method thereof | Kuan-Ting Pan, Huan-Chieh Su, Jia-Chuan You, Shi Ning Ju, Kuo-Cheng Chiang +2 more | 2023-10-24 |
| 11798884 | Contact via formation | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng | 2023-10-24 |
| 11791218 | Dipole patterning for CMOS devices | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang | 2023-10-17 |
| 11784228 | Process and structure for source/drain contacts | Meng-Huan Jao, Lin-Yu Huang, Sheng-Tsung Wang, Huan-Chieh Su, Cheng-Chi Chuang | 2023-10-10 |
| 11784233 | Integrated circuit structure with backside via rail | Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Shang-Wen Chang +3 more | 2023-10-10 |
| 11776854 | Semiconductor structure with hybrid nanostructures | Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Chao Chou | 2023-10-03 |
| 11777003 | Semiconductor structure with wraparound backside amorphous layer | Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen +3 more | 2023-10-03 |