Issued Patents All Time
Showing 176–200 of 229 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11521663 | Memory circuit and method of operating same | Yi-Ching Liu, Yih Wang | 2022-12-06 |
| 11501051 | Memory device, integrated circuit device and method | Meng-Sheng Chang, Chien-Ying Chen | 2022-11-15 |
| 11450362 | Memory device, integrated circuit device and method | Bo-Feng Young, Yu-Ming Lin, Shih-Lien Linus Lu, Han-Jong Chia, Sai-Hooi Yeong +1 more | 2022-09-20 |
| 11437386 | System and method for reducing cell area and current leakage in anti-fuse cell array | Meng-Sheng Chang, Shao-Yu Chou, Yih Wang | 2022-09-06 |
| 11424339 | Integrated chip and method of forming thereof | Meng-Han Lin | 2022-08-23 |
| 11423960 | Memory device | Meng-Sheng Chang, Yi-Ching Liu, Yih Wang | 2022-08-23 |
| 11424233 | Memory circuits and related methods | Yi-Ching Liu, Yih Wang | 2022-08-23 |
| 11417377 | Three-dimensional (3-D) write assist scheme for memory cells | Chih-Chieh Chiu, Fu-An Wu, I-Han Huang, Jung-Ping Yang | 2022-08-16 |
| 11410740 | Multi-fuse memory cell circuit and method | Meng-Sheng Chang, Shao-Yu Chou, Yih Wang | 2022-08-09 |
| 11404099 | Using split word lines and switches for reducing capacitive loading on a memory system | Sheng-Chen Wang, Meng-Han Lin, Yi-Ching Liu | 2022-08-02 |
| 11398257 | Header layout design including backside power rail | Haruki Mori, Chien-Chi TIEN, Hidehiro Fujiwara, Yen-Huei Chen, Feng-Lun CHEN | 2022-07-26 |
| 11367507 | Memory device and electronic device | Chien-Yu Huang, Cheng Hung Lee, Hua-Tai Shieh | 2022-06-21 |
| 11348929 | Memory device and method for forming the same | Hsin-Wen Su, Shih-Hao Lin, Lien Jung Hung, Ping-Wei Wang | 2022-05-31 |
| 11342341 | Integrated circuit layout, method, structure, and system | Meng-Sheng Chang, Chien-Ying Chen, Yih Wang | 2022-05-24 |
| 11315936 | Memory device and manufacturing method thereof | Meng-Sheng Chang, Yi-Hsun Chiu, Yih Wang | 2022-04-26 |
| 11257827 | Layout structure including anti-fuse cell | Meng-Sheng Chang, Wan-Hsueh Cheng, Yao-Jen Yang, Yih Wang | 2022-02-22 |
| 11256588 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Ching-Wei Wu, Donald George Mikan, Jr., Hao-I Yang +5 more | 2022-02-22 |
| 11238904 | Using embedded switches for reducing capacitive loading on a memory system | Chia-Ta Yu, Sai-Hooi Yeong, Yih Wang, Yi-Ching Liu | 2022-02-01 |
| 11200924 | Method of minimizing read-disturb-write effect of SRAM circuit and SRAM circuit thereof | Jui-Che Tsai, Yu-Hao Hsu, Yih Wang | 2021-12-14 |
| 11195567 | Balanced negative bitline voltage for a write assist circuit | Jui-Che Tsai, Chia-Cheng Chen, Yih Wang | 2021-12-07 |
| 11094387 | Multi-fuse memory cell circuit and method | Meng-Sheng Chang, Shao-Yu Chou, Yih Wang | 2021-08-17 |
| 11094701 | Layout structure of storage cell and method thereof | Meng-Sheng Chang, Yih Wang | 2021-08-17 |
| 11088151 | 4Cpp SRAM cell and array | Hidehiro Fujiwara, Yen-Huei Chen, Yih Wang | 2021-08-10 |
| 11018260 | Non-volatile memory device with reduced area | Meng-Sheng Chang, Yao-Jen Yang, Yih Wang | 2021-05-25 |
| 10978144 | Integrated circuit and operating method thereof | Hidehiro Fujiwara, Jui-Che Tsai, Yen-Huei Chen, Yih Wang | 2021-04-13 |