Issued Patents All Time
Showing 176–200 of 264 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9577049 | Semiconductor device structure and method for forming the same | Shih-Yen Lin, Chong-Rong Wu | 2017-02-21 |
| 9576908 | Interconnection structure, fabricating method thereof, and semiconductor device using the same | Yu-Hung Lin, Horng-Huei Tseng | 2017-02-21 |
| 9577101 | Source/drain regions for fin field effect transistors and methods of forming same | Kuo-Cheng Ching | 2017-02-21 |
| 9559184 | Devices including gate spacer with gap or void and methods of forming the same | Kuo-Cheng Ching, Ching-Wei Tsai, Ying-Keung Leung | 2017-01-31 |
| 9553025 | Selective Fin-shaping process | Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang | 2017-01-24 |
| 9536977 | Vertical tunneling field-effect transistor cell and fabricating the same | Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Ming Zhu | 2017-01-03 |
| 9536738 | Vertical gate all around (VGAA) devices and methods of manufacturing the same | Yu-Lien Huang, Chun-Hsiung Lin | 2017-01-03 |
| 9536772 | Fin structure of semiconductor device | Chung-Hsien Chen, Tung Ying Lee, Yu-Lien Huang | 2017-01-03 |
| 9520446 | Innovative approach of 4F2 driver formation for high-density RRAM and MRAM | Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang | 2016-12-13 |
| 9520498 | FinFET structure and method for fabricating the same | Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang | 2016-12-13 |
| 9508603 | Formation of nickel silicon and nickel germanium structure at staggered times | Chao-Hsiung Wang | 2016-11-29 |
| 9496397 | FinFet device with channel epitaxial region | Kuo-Cheng Ching, Zhi-Chang Lin, Chao-Hsiung Wang | 2016-11-15 |
| 9461110 | FETs and methods of forming FETs | Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien | 2016-10-04 |
| 9455334 | Method of forming a Fin structure of semiconductor device | Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang | 2016-09-27 |
| 9449975 | FinFET devices and methods of forming | Kuo-Cheng Ching | 2016-09-20 |
| 9418897 | Wrap around silicide for FinFETs | Kuo-Cheng Ching, Ying-Keung Leung | 2016-08-16 |
| 9406669 | Method and structure for vertical tunneling field effect transistor and planar devices | Harry-Hak-Lay Chuang, Yi-Ren Chen, Chao-Hsiung Wang, Ming Zhu | 2016-08-02 |
| 9397159 | Silicide region of gate-all-around transistor | Kuo-Cheng Ching, Chao-Hsiung Wang | 2016-07-19 |
| 9385069 | Gate contact structure for FinFET | Chao-Hsiung Wang | 2016-07-05 |
| 9385234 | FinFETs with strained well regions | Yi-Jing Lee | 2016-07-05 |
| 9379108 | Contact structure of semiconductor device | Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang +2 more | 2016-06-28 |
| 9362386 | FETs and methods for forming the same | Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee | 2016-06-07 |
| 9349841 | FinFETs and methods for forming the same | Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi Kang Liu, Yung-Ta Li +2 more | 2016-05-24 |
| 9337192 | Metal gate stack having TaAlCN layer | Shiu-Ko JangJian, Ting-Chun Wang, Chi-Cherng Jeng | 2016-05-10 |
| 9337318 | FinFET with dummy gate on non-recessed shallow trench isolation (STI) | Chao-Hsiung Wang | 2016-05-10 |