Issued Patents All Time
Showing 101–125 of 194 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9679619 | Sense amplifier with current regulating circuit | Chi-Kai Hsieh, Hong-Chen Cheng | 2017-06-13 |
| 9666253 | Dual rail memory, memory macro and associated hybrid power supply method | Jonathan Tsung-Yung Chang, Chiting Cheng, Hung-Jen Liao, Michael Patrick Clinton | 2017-05-30 |
| 9659603 | Power management circuit for an electronic device | Hektor Huang, Yangsyu Lin, Yu-Hao Hsu, Chia-En Huang, Chiting Cheng +2 more | 2017-05-23 |
| 9601162 | Memory devices with strap cells | Jonathan Tsung-Yung Chang, Chi-Ting Cheng, Hung-Jen Liao, Jhon Jhy Liaw, Yen-Huei Chen | 2017-03-21 |
| 9583181 | SRAM device capable of working in multiple low voltages without loss of performance | Pankaj Aggarwal, Jui-Che Tsai, Chien-Yuan Chen, Chiting Cheng, Hau-Tai Shieh +1 more | 2017-02-28 |
| 9490005 | Memory circuit and method for routing the memory circuit | Jui-Che Tsai, Ching-Wei Wu, Kuang Ting Chen | 2016-11-08 |
| 9489991 | Memory reading circuit, memory device and method of operating memory device | Yangsyu Lin, Hsin-Hsin Ko, Chiting Cheng, Jonathan Tsung-Yung Chang | 2016-11-08 |
| 9484350 | Semiconductor device having an inter-layer via (ILV), and method of making same | Tsung-Hsien Huang, Hong-Chen Cheng, Hung-Jen Liao | 2016-11-01 |
| 9484084 | Pulling devices for driving data lines | Hao-I Yang, Chia-En Huang, Geng-Cing Lin, Jung-Ping Yang | 2016-11-01 |
| 9449656 | Memory with bit cell header transistor | I-Han Huang, Ming-Yi Lee, Chia-En Huang, Fu-An Wu, Jung-Ping Yang | 2016-09-20 |
| 9449663 | Circuit for memory write data operation | Jung-Ping Yang, Chia-En Huang, Fu-An Wu, Chih-Chieh Chiu | 2016-09-20 |
| 9390816 | Integrated circuit having voltage mismatch reduction | Yu-Hao Hsu, Chia-En Huang, Hektor Huang, Yi-Ching Chang, Chen-Lin Yang +1 more | 2016-07-12 |
| 9389786 | Memory device with tracking mechanism | Ming-Chien Tsai, Yu-Hao Hsu, Chih-Yu Lin, Chen-Lin Yang | 2016-07-12 |
| 9355686 | Semiconductor device with more than one type of memory cell | XiuLi YANG, Liangbo Zhuang | 2016-05-31 |
| 9324453 | Memory unit and method of testing the same | Wei-jer Hsieh, Hong-Chen Cheng, Chiting Cheng, Yangsyu Lin, Jonathan Tsung-Yung Chang | 2016-04-26 |
| 9324413 | Write assist circuit, memory device and method | Hsin-Hsin Ko, Yangsyu Lin, Chiting Cheng, Jonathan Tsung-Yung Chang | 2016-04-26 |
| 9281031 | Method and apparatus for read assist to compensate for weak bit | Jonathan Tsung-Yung Chang, Chung-Cheng Chou, Hung-Jen Liao, Bin-Hau Lo | 2016-03-08 |
| 9275181 | Cell design | Chia-En Huang, Yi-Hung Tsai, Chih-Chieh Chiu, Hsiao-Lan Yang, I-Han Huang +4 more | 2016-03-01 |
| 9263123 | Memory device and a method of operating the same | Chiting Cheng, Chien-Kuo Su, Jonathan Tsung-Yung Chang | 2016-02-16 |
| 9263122 | Data-controlled auxiliary branches for SRAM cell | Chen-Lin Yang, Ming-Chien Tsai, Chung-Yi Wu | 2016-02-16 |
| 9245615 | Boost system for dual-port SRAM | Ching-Wei Wu, He-Zhou WAN, Ming-En Bu, XiuLi YANG, Mu-Jen Huang | 2016-01-26 |
| 9240233 | Integrated circuit having voltage mismatch reduction | Yu-Hao Hsu, Chia-En Huang, Hektor Huang, Yi-Ching Chang, Chen-Lin Yang +1 more | 2016-01-19 |
| 9218262 | Dynamic memory cell replacement using column redundancy | Fu-An Wu, Jung-Ping Yang, Chia-En Huang | 2015-12-22 |
| 9208855 | Weak bit compensation for static random access memory | — | 2015-12-08 |
| 9183907 | Vccmin for a dual port synchronous random access memory (DPSRAM) cell utilized as a single port synchronous random access memory (SPSRAM) cell | Ching-Wei Wu, Chia-Cheng Chen | 2015-11-10 |