Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11734142 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald George Mikan, Jr. +5 more | 2023-08-22 |
| 11256588 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald George Mikan, Jr. +5 more | 2022-02-22 |
| 10705934 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald George Mikan, Jr. +5 more | 2020-07-07 |
| 9978443 | Method of controlling auxiliary branches for SRAM cell | Chen-Lin Yang, Chung-Yi Wu, Cheng Hung Lee | 2018-05-22 |
| 9389786 | Memory device with tracking mechanism | Yu-Hao Hsu, Chih-Yu Lin, Chen-Lin Yang, Cheng Hung Lee | 2016-07-12 |
| 9263122 | Data-controlled auxiliary branches for SRAM cell | Chen-Lin Yang, Chung-Yi Wu, Cheng Hung Lee | 2016-02-16 |
| 9111595 | Memory device with tracking wordline voltage level circuit and method | Yu-Hao Hsu, Chen-Lin Yang | 2015-08-18 |
| 8804445 | Oscillato based on a 6T SRAM for measuring the bias temperature instability | Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Yi-Wei Lin, Hao-I Yang +4 more | 2014-08-12 |
| 8582378 | Threshold voltage measurement device | Ching-Te Chuang, Shyh-Jye Jou, Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin +4 more | 2013-11-12 |