HC

Hao-Jan Chao

ST Syntest Technologies: 10 patents #11 of 31Top 40%
Overall (All Time): #514,173 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Showing 1–10 of 10 patents

Patent #TitleCo-InventorsDate
9057763 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang +1 more 2015-06-16
9026875 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang +1 more 2015-05-05
8769359 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test Luang-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang +1 more 2014-07-01
8458544 Multiple-capture DFT system to reduce peak capture power during self-test or scan test Laung-Terng Wang, Shianling Wu 2013-06-04
8091002 Multiple-capture DFT system to reduce peak capture power during self-test or scan test Laung-Terng Wang, Shianling Wu, Zhigang Jiang, Jinsong Liu, Lizhen Yu +3 more 2012-01-03
7779323 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang +1 more 2010-08-17
7284175 Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques Laung-Terng Wang, Ming-Tung Chang, Xiaoqing Wen, Po-Ching Hsu 2007-10-16
7191373 Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques Laung-Terng Wang, Ming-Tung Chang, Shyh-Horng Lin, Jaehee Lee, Hsin-Po Wang +6 more 2007-03-13
7058869 Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits Khader S. Abdel-Hafez, Xiaoqing Wen, Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao +1 more 2006-06-06
7007213 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang +1 more 2006-02-28