Issued Patents All Time
Showing 101–125 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8847324 | Increasing ION /IOFF ratio in FinFETs and nano-wires | Munkang Choi, Xi-Wei Lin | 2014-09-30 |
| 8813012 | Self-aligned via interconnect using relaxed patterning exposure | Michael L. Rieger | 2014-08-19 |
| 8786057 | Integrated circuit on corrugated substrate | Tsu-Jae King | 2014-07-22 |
| 8762924 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2014-06-24 |
| 8723268 | N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch | Deepak D. Sherlekar | 2014-05-13 |
| 8713510 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2014-04-29 |
| 8701054 | Boosting transistor performance with non-rectangular channels | Munkang Choi, Xi-Wei Lin | 2014-04-15 |
| 8686512 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Dipankar Pramanik, Xi-Wei Lin | 2014-04-01 |
| 8661387 | Placing transistors in proximity to through-silicon vias | James David Sproch, Xiaopeng Xu, Aditya Pradeep Karmarkar | 2014-02-25 |
| 8661398 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2014-02-25 |
| 8615728 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2013-12-24 |
| 8609550 | Methods for manufacturing integrated circuit devices having features with reduced edge curvature | Lars Bomholt | 2013-12-17 |
| 8595661 | N-channel and p-channel finFET cell architecture | Jamil Kawa, Deepak D. Sherlekar | 2013-11-26 |
| 8561003 | N-channel and P-channel finFET cell architecture with inter-block insulator | Jamil Kawa, Deepak D. Sherlekar | 2013-10-15 |
| 8560995 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2013-10-15 |
| 8413096 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2013-04-02 |
| 8407634 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2013-03-26 |
| 8362622 | Method and apparatus for placing transistors in proximity to through-silicon vias | James David Sproch, Xiaopeng Xu, Aditya Pradeep Karmarkar | 2013-01-29 |
| 8354736 | Reclaiming usable integrated circuit chip area near through-silicon vias | — | 2013-01-15 |
| 8349668 | Stress-enhanced performance of a FinFET using surface/channel orientations and strained capping layers | Tsu-Jae King Liu | 2013-01-08 |
| 8347252 | Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array | Dipankar Pramanik | 2013-01-01 |
| 8219961 | Method for compensation of process-induced performance variation in a MOSFET integrated circuit | Dipankar Pramanik, Kishore Singhal, Xi-Wei Lin | 2012-07-10 |
| 8086990 | Method of correlating silicon stress to device instance parameters for circuit simulation | Xi-Wei Lin, Dipankar Pramanik | 2011-12-27 |
| 8069430 | Stress-managed revision of integrated circuit layouts | Xi-Wei Lin, Dipankar Pramanik | 2011-11-29 |
| 8035168 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Dipankar Pramanik, Xi-Wei Lin | 2011-10-11 |