Issued Patents All Time
Showing 126–148 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7996795 | Method and apparatus for performing stress modeling of integrated circuit material undergoing material conversion | Xiaopeng Xu | 2011-08-09 |
| 7968413 | Methods for forming a transistor | Faran Nouri, Lori D. Washington | 2011-06-28 |
| 7960232 | Methods of designing an integrated circuit on corrugated substrate | Tsu-Jae King | 2011-06-14 |
| 7949985 | Method for compensation of process-induced performance variation in a MOSFET integrated circuit | Dipankar Pramanik, Kishore Singhal, Xi-Wei Lin | 2011-05-24 |
| 7939862 | Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers | Tsu-Jae King Liu | 2011-05-10 |
| 7926018 | Method and apparatus for generating a layout for a transistor | Xi-Wei Lin, Mark Rubin | 2011-04-12 |
| 7897479 | Managing integrated circuit stress using dummy diffusion regions | Xi-Wei Lin, Dipankar Pramanik | 2011-03-01 |
| 7863146 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Dipankar Pramanik, Xi-Wei Lin | 2011-01-04 |
| 7833869 | Methods for forming a transistor | Faran Nouri, Lori D. Washington | 2010-11-16 |
| 7767515 | Managing integrated circuit stress using stress adjustment trenches | Dipankar Pramanik, Xi-Wei Lin | 2010-08-03 |
| 7705406 | Transistor array with selected subset having suppressed layout sensitivity of threshold voltage | Dipankar Pramanik | 2010-04-27 |
| 7691693 | Method for suppressing layout sensitivity of threshold voltage in a transistor array | Dipankar Pramanik | 2010-04-06 |
| 7681164 | Method and apparatus for placing an integrated circuit device within an integrated circuit layout | Xi-Wei Lin | 2010-03-16 |
| 7600207 | Stress-managed revision of integrated circuit layouts | Dipankar Pramanik, Xi-Wei Lin | 2009-10-06 |
| 7584438 | Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array | Dipankar Pramanik | 2009-09-01 |
| 7542891 | Method of correlating silicon stress to device instance parameters for circuit simulation | Xi-Wei Lin, Dipankar Pramanik | 2009-06-02 |
| 7528465 | Integrated circuit on corrugated substrate | Tsu-Jae King | 2009-05-05 |
| 7484198 | Managing integrated circuit stress using dummy diffusion regions | Xi-Wei Lin, Dipankar Pramanik | 2009-01-27 |
| 7413957 | Methods for forming a transistor | Faran Nouri, Lori D. Washington | 2008-08-19 |
| 7302375 | Simulation of processes, devices and circuits by a modified newton method | Andrey Kucherov | 2007-11-27 |
| 7265008 | Method of IC production using corrugated substrate | Tsu-Jae King | 2007-09-04 |
| 7247887 | Segmented channel MOS transistor | Tsu-Jae King | 2007-07-24 |
| 7190050 | Integrated circuit on corrugated substrate | Tsu-Jae King | 2007-03-13 |