Issued Patents All Time
Showing 76–100 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9400862 | Cells having transistors and interconnects including nanowires or 2D material strips | Jamil Kawa | 2016-07-26 |
| 9379018 | Increasing Ion/Ioff ratio in FinFETs and nano-wires | Munkang Choi, Xi-Wei Lin | 2016-06-28 |
| 9379183 | Methods for manufacturing integrated circuit devices having features with reduced edge curvature | Lars Bomholt | 2016-06-28 |
| 9378320 | Array with intercell conductors including nanowires or 2D material strips | Jamil Kawa | 2016-06-28 |
| 9361418 | Nanowire or 2D material strips interconnects in an integrated circuit cell | Jamil Kawa | 2016-06-07 |
| 9287253 | Method and apparatus for floating or applying voltage to a well of an integrated circuit | Jamil Kawa, James David Sproch, Robert B. Lefferts | 2016-03-15 |
| 9275182 | Placing transistors in proximity to through-silicon vias | James David Sproch, Xiaopeng Xu, Aditya Pradeep Karmarkar | 2016-03-01 |
| 9257429 | N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch | Deepak D. Sherlekar | 2016-02-09 |
| 9209129 | Self-aligned via interconnect using relaxed patterning exposure | Michael L. Rieger | 2015-12-08 |
| 9190346 | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits | Jamil Kawa | 2015-11-17 |
| 9189580 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2015-11-17 |
| 9184110 | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits | Jamil Kawa | 2015-11-10 |
| 9177894 | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits | Jamil Kawa | 2015-11-03 |
| 9152750 | Methods for manufacturing integrated circuit devices having features with reduced edge curvature | Lars Bomholt | 2015-10-06 |
| 9141737 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2015-09-22 |
| 9076673 | FinFET cell architecture with power traces | Jamil Kawa, Deepak D. Sherlekar | 2015-07-07 |
| 9064808 | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same | Lars Bomholt | 2015-06-23 |
| 9048121 | FinFET cell architecture with insulator structure | Jamil Kawa, Deepak D. Sherlekar | 2015-06-02 |
| 9003348 | Placing transistors in proximity to through-silicon vias | James David Sproch, Xiaopeng Xu, Aditya Pradeep Karmarkar | 2015-04-07 |
| 8987828 | N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch | Deepak D. Sherlekar | 2015-03-24 |
| 8964453 | SRAM layouts | Xi-Wei Lin | 2015-02-24 |
| 8924908 | FinFET cell architecture with power traces | Jamil Kawa, Deepak D. Sherlekar | 2014-12-30 |
| 8901615 | N-channel and P-channel end-to-end finfet cell architecture | — | 2014-12-02 |
| 8881073 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2014-11-04 |
| 8869078 | Boosting transistor performance with non-rectangular channels | Munkang Choi, Xi-Wei Lin | 2014-10-21 |