Issued Patents All Time
Showing 51–75 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10312229 | Memory cells including vertical nanowire transistors | Jamil Kawa, Thu Nguyen | 2019-06-04 |
| 10256223 | Cells having transistors and interconnects including nanowires or 2D material strips | Jamil Kawa | 2019-04-09 |
| 10256293 | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same | Lars Bomholt | 2019-04-09 |
| 10121896 | FinFet with heterojunction and improved channel control | Stephen Lee Smith, Qiang Lu | 2018-11-06 |
| 10102318 | Atomic scale grid for modeling semiconductor structures and fabrication processes | Stephen Lee Smith | 2018-10-16 |
| 10049173 | Parameter extraction of DFT | Jie Liu, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam +1 more | 2018-08-14 |
| 10037397 | Memory cell including vertical transistors and horizontal nanowire bit lines | Jamil Kawa | 2018-07-31 |
| 10032859 | Methods for manufacturing integrated circuit devices having features with reduced edge curvature | Lars Bomholt | 2018-07-24 |
| 9953990 | One-time programmable memory using rupturing of gate insulation | Andrew E. Horch, Jamil Kawa | 2018-04-24 |
| 9917018 | Method and apparatus with channel stop doped devices | — | 2018-03-13 |
| 9881111 | Simulation scaling with DFT and non-DFT | Jie Liu, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam +1 more | 2018-01-30 |
| 9852242 | Atomic scale grid for modeling semiconductor structures and fabrication processes | Stephen Lee Smith | 2017-12-26 |
| 9836563 | Iterative simulation with DFT and non-DFT | Jie Liu, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam +1 more | 2017-12-05 |
| 9817928 | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits | Jamil Kawa | 2017-11-14 |
| 9786734 | Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same | Lars Bomholt | 2017-10-10 |
| 9735227 | 2D material super capacitors | Jamil Kawa | 2017-08-15 |
| 9727675 | Parameter extraction of DFT | Jie Liu, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam +1 more | 2017-08-08 |
| 9728528 | Method and apparatus for floating or applying voltage to a well of an integrated circuit | Jamil Kawa, James David Sproch, Robert B. Lefferts | 2017-08-08 |
| 9691764 | FinFET cell architecture with power traces | Jamil Kawa, Deepak D. Sherlekar | 2017-06-27 |
| 9691768 | Nanowire or 2D material strips interconnects in an integrated circuit cell | Jamil Kawa | 2017-06-27 |
| 9646966 | N-channel and P-channel end-to-end finFET cell architecture | — | 2017-05-09 |
| 9547740 | Methods for fabricating high-density integrated circuit devices | Xi-Wei Lin | 2017-01-17 |
| 9472423 | Method for suppressing lattice defects in a semiconductor substrate | Dipankar Pramanik | 2016-10-18 |
| 9465897 | Analysis of stress impact on transistor performance | Dipankar Pramanik | 2016-10-11 |
| 9418189 | SRAM layouts | Xi-Wei Lin | 2016-08-16 |