Deepak D. Sherlekar — 36 Patents at Synopsys

Deepak D. Sherlekar has been granted 36 US patents while listed as an inventor at Synopsys. The first was granted in 1999 and the most recent in March 2025. Deepak D. Sherlekar ranks #92,222 of 4,157,543 US inventors in our database (top 2.2%). Patent records list Deepak D. Sherlekar in Cupertino, CA, US.

Issued Patents All Time

Showing 1–25 of 36 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12248744	Poly-bit cells	Shanie George, Shi-An Chen, Vahe Harutyunyan	2025-03-11
12231125	Power efficient retention flip flop circuit	Sai Yaswanth Divvela, Amit Verma, Basannagouda Somanath Reddy	2025-02-18
12086523	Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries	Victor Moroz	2024-09-10	$234,933,000
12079558	On-the-fly multi-bit flip flop generation	Basannagouda Somanath Reddy, Shanie George	2024-09-03	$143,956,000
11847396	Integrated circuit design using multi-bit combinational cells	Mayank Jain, Mohammad Ziaullah Khan, Guilherme Augusto Flach, Linuo Xue, Jeff Ku +1 more	2023-12-19	$220,897,000
11837280	CFET architecture for balancing logic library and SRAM bitcell	Victor Moroz, Jamil Kawa	2023-12-05	$70,386,000
11790150	Placement and simulation of cell in proximity to cell with diffusion break	Shanie George	2023-10-17	$141,245,000
11681848	On-the-fly multi-bit flip flop generation	Basannagouda Somanath Reddy, Shanie George	2023-06-20	$184,412,000
11657205	Construction, modeling, and mapping of multi-output cells	Mohammad Ziaullah Khan	2023-05-23	$135,845,000
11416661	Automatic derivation of integrated circuit cell mapping rules in an engineering change order flow	Kai Wang, Wencai Zheng, Xiaolin Yuan	2022-08-16	$181,236,000
11403454	Placement and simulation of cell in proximity to cell with diffusion break	Shanie George	2022-08-02	$73,386,000
11328109	Refining multi-bit flip flops mapping without explicit de-banking and re-banking	Mohammad Ziaullah Khan, Channakeshav Ananth, Muniraj Ramamurthy	2022-05-10	$80,948,000
10990722	FinFET cell architecture with insulator structure	Jamil Kawa, Victor Moroz	2021-04-27	$59,323,000
10205440	Retention flip-flop circuits for low power applications	Basannagouda Somanath Reddy, Princy K. Varghese	2019-02-12	$9,923,000
9691764	FinFET cell architecture with power traces	Jamil Kawa, Victor Moroz	2017-06-27	$8,946,000
9257429	N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch	Victor Moroz	2016-02-09	$12,508,000
9076673	FinFET cell architecture with power traces	Jamil Kawa, Victor Moroz	2015-07-07	$12,606,000
9048121	FinFET cell architecture with insulator structure	Jamil Kawa, Victor Moroz	2015-06-02	$8,176,000
8987828	N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch	Victor Moroz	2015-03-24	$7,348,000
8941150	Power routing in standard cells	Vahe Hovsepyan	2015-01-27	$21,973,000
8924908	FinFET cell architecture with power traces	Jamil Kawa, Victor Moroz	2014-12-30	$4,224,000
8742464	Power routing in standard cells	Vahe Hovsepyan	2014-06-03	$2,735,000
8723268	N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch	Victor Moroz	2014-05-13	$3,683,000
8631374	Cell architecture for increasing transistor size	—	2014-01-14	$6,672,000
8612914	Pin routing in standard cells	Vahe Hovsepyan	2013-12-17	$4,039,000

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Deepak D. Sherlekar — 36 Patents

Issued Patents All Time

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