Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12248744 | Poly-bit cells | Shanie George, Shi-An Chen, Vahe Harutyunyan | 2025-03-11 |
| 12231125 | Power efficient retention flip flop circuit | Sai Yaswanth Divvela, Amit Verma, Basannagouda Somanath Reddy | 2025-02-18 |
| 12086523 | Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries | Victor Moroz | 2024-09-10 |
| 12079558 | On-the-fly multi-bit flip flop generation | Basannagouda Somanath Reddy, Shanie George | 2024-09-03 |
| 11847396 | Integrated circuit design using multi-bit combinational cells | Mayank Jain, Mohammad Ziaullah Khan, Guilherme Augusto Flach, Linuo Xue, Jeff Ku +1 more | 2023-12-19 |
| 11837280 | CFET architecture for balancing logic library and SRAM bitcell | Victor Moroz, Jamil Kawa | 2023-12-05 |
| 11790150 | Placement and simulation of cell in proximity to cell with diffusion break | Shanie George | 2023-10-17 |
| 11681848 | On-the-fly multi-bit flip flop generation | Basannagouda Somanath Reddy, Shanie George | 2023-06-20 |
| 11657205 | Construction, modeling, and mapping of multi-output cells | Mohammad Ziaullah Khan | 2023-05-23 |
| 11416661 | Automatic derivation of integrated circuit cell mapping rules in an engineering change order flow | Kai Wang, Wencai Zheng, Xiaolin Yuan | 2022-08-16 |
| 11403454 | Placement and simulation of cell in proximity to cell with diffusion break | Shanie George | 2022-08-02 |
| 11328109 | Refining multi-bit flip flops mapping without explicit de-banking and re-banking | Mohammad Ziaullah Khan, Channakeshav Ananth, Muniraj Ramamurthy | 2022-05-10 |
| 10990722 | FinFET cell architecture with insulator structure | Jamil Kawa, Victor Moroz | 2021-04-27 |
| 10205440 | Retention flip-flop circuits for low power applications | Basannagouda Somanath Reddy, Princy K. Varghese | 2019-02-12 |
| 9691764 | FinFET cell architecture with power traces | Jamil Kawa, Victor Moroz | 2017-06-27 |
| 9257429 | N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch | Victor Moroz | 2016-02-09 |
| 9076673 | FinFET cell architecture with power traces | Jamil Kawa, Victor Moroz | 2015-07-07 |
| 9048121 | FinFET cell architecture with insulator structure | Jamil Kawa, Victor Moroz | 2015-06-02 |
| 8987828 | N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch | Victor Moroz | 2015-03-24 |
| 8941150 | Power routing in standard cells | Vahe Hovsepyan | 2015-01-27 |
| 8924908 | FinFET cell architecture with power traces | Jamil Kawa, Victor Moroz | 2014-12-30 |
| 8742464 | Power routing in standard cells | Vahe Hovsepyan | 2014-06-03 |
| 8723268 | N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch | Victor Moroz | 2014-05-13 |
| 8631374 | Cell architecture for increasing transistor size | — | 2014-01-14 |
| 8612914 | Pin routing in standard cells | Vahe Hovsepyan | 2013-12-17 |