Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Victor Moroz — 149 Patents

SYSynopsys: 145 patents #1 of 2,302Top 1%
Applied Materials: 3 patents #3,025 of 7,310Top 45%
Saratoga, CA: #31 of 2,933 inventorsTop 2%
California: #1,012 of 386,348 inventorsTop 1%
Overall (All Time): #6,316 of 4,157,543Top 1%
149 Patents All Time
Victor Moroz has been granted 149 US patents while listed as an inventor at Synopsys. The first was granted in 2007 and the most recent in October 2025. Victor Moroz ranks #6,316 of 4,157,543 US inventors in our database (top 0.15%). Patent records list Victor Moroz in Saratoga, CA, US.

Issued Patents All Time

Showing 1–25 of 149 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12453129 Stacked nanosheet device for process and performance optimization Xi-Wei Lin, Zumao Qin, Plamen Asenov 2025-10-21
12368100 Interconnects, inductors, transformers, and power architectures for circuits Jamil Kawa, Stephen Robert Whiteley 2025-07-22
12300493 Isolating ion implantation of silicon channels for integrated circuit layout Salvatore Amoroso, Jr., Plamen Asenov 2025-05-13
12086523 Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries Deepak D. Sherlekar 2024-09-10 $234,933,000
12080608 Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (CFET) Xi-Wei Lin 2024-09-03 $143,956,000
12041858 Josephson junction structures Jamil Kawa, Stephen Robert Whiteley 2024-07-16 $143,372,000
11984384 Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery network Xi-Wei Lin 2024-05-14 $176,735,000
11937507 Power harvesting for integrated circuits Jamil Kawa 2024-03-19 $573,092,000
11915984 Forming a wrap-around contact to connect a source or drain epitaxial growth of a complimentary field effect transistor (CFET) to a buried power rail (BPR) of the CFET Xi-Wei Lin 2024-02-27 $167,423,000
11894049 CFET SRAM cell utilizing 8 transistors Plamen Asenov 2024-02-06 $250,737,000
11837280 CFET architecture for balancing logic library and SRAM bitcell Deepak D. Sherlekar, Jamil Kawa 2023-12-05 $70,386,000
11776816 Fin patterning to reduce fin collapse and transistor leakage Xi-Wei Lin 2023-10-03 $136,241,000
11742247 Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET) Xi-Wei Lin 2023-08-29 $101,295,000
11710634 Fabrication technique for forming ultra-high density integrated circuit components Xi-Wei Lin 2023-07-25 $198,015,000
11521985 Electro-thermal method to manufacture monocrystalline vertically oriented silicon channels for three-dimensional (3D) NAND memories Salvatore Amoroso, Jr. 2022-12-06 $170,177,000
11489102 Josephson junction structures Jamil Kawa, Stephen Robert Whiteley 2022-11-01 $141,038,000
11342492 Josephson junction structures Jamil Kawa, Stephen Robert Whiteley 2022-05-24 $47,952,000
11264458 Crystal orientation engineering to achieve consistent nanowire shapes Ignacio Martin-Bragado 2022-03-01 $273,499,000
11249813 Adaptive parallelization for multi-scale simulation Stephen Lee Smith, Michael C. Shaughnessy-Culver, Jie Liu, Yong-Seog Oh, Pratheep Balasingam +1 more 2022-02-15 $130,532,000
11188699 Placement and routing of cells using cell-level layout-dependent stress effects 2021-11-30 $60,918,000
11177317 Power harvesting for integrated circuits Jamil Kawa 2021-11-16 $102,912,000
11139402 Crystal orientation engineering to achieve consistent nanowire shapes Ignacio Martin-Bragado 2021-10-05 $130,968,000
11133045 Magnetoresistive random access memory (MRAM) bit cell with a narrow write window distribution Jamil Kawa 2021-09-28 $89,414,000
11068631 First principles design automation tool Yong-Seog Oh, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Jie Liu, Pratheep Balasingam +1 more 2021-07-20 $249,912,000
10990722 FinFET cell architecture with insulator structure Jamil Kawa, Deepak D. Sherlekar 2021-04-27 $59,323,000