Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11249813 | Adaptive parallelization for multi-scale simulation | Michael C. Shaughnessy-Culver, Jie Liu, Victor Moroz, Yong-Seog Oh, Pratheep Balasingam +1 more | 2022-02-15 |
| 11068631 | First principles design automation tool | Yong-Seog Oh, Michael C. Shaughnessy-Culver, Jie Liu, Victor Moroz, Pratheep Balasingam +1 more | 2021-07-20 |
| 10831957 | Simulation scaling with DFT and non-DFT | Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Yong-Seog Oh, Pratheep Balasingam +1 more | 2020-11-10 |
| 10776560 | Mapping intermediate material properties to target properties to screen materials | Victor Moroz, Yong-Seog Oh, Michael C. Shaughnessy-Culver, Jie Liu, Terry Sylvan Kam-Chiu Ma | 2020-09-15 |
| 10756212 | FinFET with heterojunction and improved channel control | Victor Moroz, Qiang Lu | 2020-08-25 |
| 10706209 | Estimation of effective channel length for FinFETs and nano-wires | Victor Moroz, Yong-Seog Oh, Michael C. Shaughnessy-Culver, Jie Liu | 2020-07-07 |
| 10685156 | Multi-scale simulation including first principles band structure extraction | Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Yong-Seog Oh, Pratheep Balasingam +1 more | 2020-06-16 |
| 10606968 | Atomic scale grid for modeling semiconductor structures and fabrication processes | Victor Moroz | 2020-03-31 |
| 10516725 | Characterizing target material properties based on properties of similar materials | Victor Moroz, Yong-Seog Oh, Jie Liu, Michael C. Shaughnessy-Culver, Terry Sylvan Kam-Chiu Ma | 2019-12-24 |
| 10489212 | Adaptive parallelization for multi-scale simulation | Michael C. Shaughnessy-Culver, Jie Liu, Victor Moroz, Yong-Seog Oh, Pratheep Balasingam +1 more | 2019-11-26 |
| 10417373 | Estimation of effective channel length for FinFETs and nano-wires | Victor Moroz, Yong-Seog Oh, Michael C. Shaughnessy-Culver, Jie Liu | 2019-09-17 |
| 10402520 | First principles design automation tool | Yong-Seog Oh, Michael C. Shaughnessy-Culver, Jie Liu, Victor Moroz, Pratheep Balasingam +1 more | 2019-09-03 |
| 10121896 | FinFet with heterojunction and improved channel control | Victor Moroz, Qiang Lu | 2018-11-06 |
| 10102318 | Atomic scale grid for modeling semiconductor structures and fabrication processes | Victor Moroz | 2018-10-16 |
| 10049173 | Parameter extraction of DFT | Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Yong-Seog Oh, Pratheep Balasingam +1 more | 2018-08-14 |
| 9881111 | Simulation scaling with DFT and non-DFT | Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Yong-Seog Oh, Pratheep Balasingam +1 more | 2018-01-30 |
| 9852242 | Atomic scale grid for modeling semiconductor structures and fabrication processes | Victor Moroz | 2017-12-26 |
| 9836563 | Iterative simulation with DFT and non-DFT | Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Yong-Seog Oh, Pratheep Balasingam +1 more | 2017-12-05 |
| 9727675 | Parameter extraction of DFT | Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Yong-Seog Oh, Pratheep Balasingam +1 more | 2017-08-08 |
| 9530027 | Device lock for transit | Shahrokh Shahidzadeh, Venkatesh Ramamurthy, Reinhard R. Steffens, Gyan Prakash, Christian von Reventlow +1 more | 2016-12-27 |
| 6259720 | Versatile digital signal processing system | John Michael Buss, James Douglas Dworkin | 2001-07-10 |
| 5852730 | Hybrid instruction set for versatile digital signal processing system | John Michael Buss, James Douglas Dworkin | 1998-12-22 |
| 5752012 | Computational array with self timed computational element and method of self timed calculation | — | 1998-05-12 |
| 5726924 | Exponentiation circuit utilizing shift means and method of using same | John Michael Buss, James Douglas Dworkin, Scott Edward Lloyd, Shaowei Pan, Shay-Ping T. Wang | 1998-03-10 |
| 5608663 | Computational array circuit for providing parallel multiplication | — | 1997-03-04 |