Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8595661 | N-channel and p-channel finFET cell architecture | Jamil Kawa, Victor Moroz | 2013-11-26 |
| 8561003 | N-channel and P-channel finFET cell architecture with inter-block insulator | Jamil Kawa, Victor Moroz | 2013-10-15 |
| 8513978 | Power routing in standard cell designs | — | 2013-08-20 |
| 8392862 | Structures and methods for optimizing power consumption in an integrated chip design | Oscar M. Siguenza, Duane G. Breid, Gene Sluss, Mike Colwell | 2013-03-05 |
| 8132142 | Various methods and apparatuses to route multiple power rails to a cell | Gene Sluss, Tushar R. Gheewala | 2012-03-06 |
| 7989849 | Apparatuses and methods for efficient power rail structures for cell libraries | Darrell Heinecke, Eswar Veluri | 2011-08-02 |
| 7603634 | Various methods and apparatuses to preserve a logic state for a volatile latch circuit | Gene Sluss, Tushar R. Gheewala | 2009-10-13 |
| 7219324 | Various methods and apparatuses to route multiple power rails to a cell | Gene Sluss, Tushar R. Gheewala | 2007-05-15 |
| 7069522 | Various methods and apparatuses to preserve a logic state for a volatile latch circuit | Gene Sluss, Tushar R. Gheewala | 2006-06-27 |
| 6617621 | Gate array architecture using elevated metal levels for customization | Tushar R. Gheewala, Duane G. Breid, Michael J. Colwell | 2003-09-09 |
| 5943243 | Method and system for removing hardware design overlap | Craig R. Selinger | 1999-08-24 |