Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8392862 | Structures and methods for optimizing power consumption in an integrated chip design | Oscar M. Siguenza, Gene Sluss, Deepak D. Sherlekar, Mike Colwell | 2013-03-05 |
| 7129562 | Dual-height cell with variable width power rail architecture | Tushar R. Gheewala, Michael J. Colwell, Henry H. Yang | 2006-10-31 |
| 6838713 | Dual-height cell with variable width power rail architecture | Tushar R. Gheewala, Michael J. Colwell, Henry H. Yang | 2005-01-04 |
| 6617621 | Gate array architecture using elevated metal levels for customization | Tushar R. Gheewala, Deepak D. Sherlekar, Michael J. Colwell | 2003-09-09 |
| 6385761 | Flexible width cell layout architecture | — | 2002-05-07 |
| 5860092 | Apparatus and method for addressing a cache memory in a computer system utilizing cache tag memory with integrated adder and pre-decode circuit | Roger Roisen, Ronald D. Isliefson | 1999-01-12 |
| 5619420 | Semiconductor cell having a variable transistor width | — | 1997-04-08 |