Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8392862 | Structures and methods for optimizing power consumption in an integrated chip design | Oscar M. Siguenza, Duane G. Breid, Deepak D. Sherlekar, Mike Colwell | 2013-03-05 |
| 8132142 | Various methods and apparatuses to route multiple power rails to a cell | Deepak D. Sherlekar, Tushar R. Gheewala | 2012-03-06 |
| 7603634 | Various methods and apparatuses to preserve a logic state for a volatile latch circuit | Deepak D. Sherlekar, Tushar R. Gheewala | 2009-10-13 |
| 7219324 | Various methods and apparatuses to route multiple power rails to a cell | Deepak D. Sherlekar, Tushar R. Gheewala | 2007-05-15 |
| 7069522 | Various methods and apparatuses to preserve a logic state for a volatile latch circuit | Deepak D. Sherlekar, Tushar R. Gheewala | 2006-06-27 |
| 4730273 | On-chip programmability verification circuit for programmable read only memory having lateral fuses | — | 1988-03-08 |
| 4716547 | Current switch for programming vertical fuses of a read only memory | Ira E. Baskett | 1987-12-29 |