Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8132142 | Various methods and apparatuses to route multiple power rails to a cell | Deepak D. Sherlekar, Gene Sluss | 2012-03-06 |
| 7603634 | Various methods and apparatuses to preserve a logic state for a volatile latch circuit | Gene Sluss, Deepak D. Sherlekar | 2009-10-13 |
| 7219324 | Various methods and apparatuses to route multiple power rails to a cell | Deepak D. Sherlekar, Gene Sluss | 2007-05-15 |
| 7129562 | Dual-height cell with variable width power rail architecture | Michael J. Colwell, Henry H. Yang, Duane G. Breid | 2006-10-31 |
| 7069522 | Various methods and apparatuses to preserve a logic state for a volatile latch circuit | Gene Sluss, Deepak D. Sherlekar | 2006-06-27 |
| 6991947 | Hybrid semiconductor circuit with programmable intraconnectivity | — | 2006-01-31 |
| 6838713 | Dual-height cell with variable width power rail architecture | Michael J. Colwell, Henry H. Yang, Duane G. Breid | 2005-01-04 |
| 6617621 | Gate array architecture using elevated metal levels for customization | Duane G. Breid, Deepak D. Sherlekar, Michael J. Colwell | 2003-09-09 |
| 6445065 | Routing driven, metal programmable integrated circuit architecture with multiple types of core cells | Henry H. Yang | 2002-09-03 |
| 6091090 | Power and signal routing technique for gate array design | — | 2000-07-18 |
| 5923059 | Integrated circuit cell architecture and routing scheme | — | 1999-07-13 |
| 5923060 | Reduced area gate array cell design based on shifted placement of alternate rows of cells | — | 1999-07-13 |
| 5898194 | Integrated circuit cell architecture and routing scheme | — | 1999-04-27 |
| 5799021 | Method for direct access test of embedded cells and customization logic | — | 1998-08-25 |
| 5495486 | Method and apparatus for testing integrated circuits | — | 1996-02-27 |
| 5471152 | Storage element for delay testing | Rustam Mehta, Prab Varma | 1995-11-28 |
| 5436801 | Method and structure for routing power for optimum cell utilization with two and three level metal in a partially predesigned integrated circuit | Rustam Mehta, Timothy Saxe | 1995-07-25 |
| 5230001 | Method for testing a sequential circuit by splicing test vectors into sequential test pattern | Susheel J. Chandra | 1993-07-20 |
| 5206862 | Method and apparatus for locally deriving test signals from previous response signals | Susheel J. Chandra | 1993-04-27 |
| 5202624 | Interface between IC operational circuitry for coupling test signal from internal test matrix | Hector R. Sucar | 1993-04-13 |
| 5157627 | Method and apparatus for setting desired signal level on storage element | — | 1992-10-20 |
| 5065090 | "Method for testing integrated circuits having a grid-based, ""cross-check"" t e" | — | 1991-11-12 |
| 4937826 | Method and apparatus for sensing defects in integrated circuit elements | Robert J. Lipp | 1990-06-26 |
| 4845542 | Interconnect for layered integrated circuit assembly | Steve Joseph Bezuk, Stephen A. Campbell, Robert J. Baseman | 1989-07-04 |
| 4749947 | "Grid-based, ""cross-check"" test structure for testing integrated circuits" | — | 1988-06-07 |