Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12309135 | Federated login with centralized control | Seungyeop Han, Hao Wu, Tiffany Lin | 2025-05-20 |
| 12131106 | Layout method and apparatus based on genetic algorithm | Limei Liu, Chuanpeng YU | 2024-10-29 |
| 11722475 | Federated login with centralized control | Seungyeop Han, Hao Wu, Tiffany Lin | 2023-08-08 |
| 9275182 | Placing transistors in proximity to through-silicon vias | James David Sproch, Victor Moroz, Aditya Pradeep Karmarkar | 2016-03-01 |
| 9003348 | Placing transistors in proximity to through-silicon vias | James David Sproch, Victor Moroz, Aditya Pradeep Karmarkar | 2015-04-07 |
| 8776005 | Modeling mechanical behavior with layout-dependent material properties | Dasarapu Vinay Kumar, Xi-Wei Lin | 2014-07-08 |
| 8661387 | Placing transistors in proximity to through-silicon vias | James David Sproch, Victor Moroz, Aditya Pradeep Karmarkar | 2014-02-25 |
| 8362622 | Method and apparatus for placing transistors in proximity to through-silicon vias | James David Sproch, Victor Moroz, Aditya Pradeep Karmarkar | 2013-01-29 |
| 7996795 | Method and apparatus for performing stress modeling of integrated circuit material undergoing material conversion | Victor Moroz | 2011-08-09 |
| 7543254 | Method and apparatus for fast identification of high stress regions in integrated circuit structure | Dipankar Pramanik | 2009-06-02 |