Robert Walker — 21 Patents at Synopsys

Robert Walker has been granted 21 US patents while listed as an inventor at Synopsys. The first was granted in 1997 and the most recent in March 2021. Robert Walker ranks #201,324 of 4,157,543 US inventors in our database (top 4.8%). Patent records list Robert Walker in Boulder, CO, US.

Issued Patents All Time

Showing 1–21 of 21 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
10936772	Methods for incremental circuit physical synthesis	Mahesh A. Iyer, Vasudeva M. Kamath	2021-03-02
10339241	Methods for incremental circuit design legalization during physical synthesis	Mahesh A. Iyer	2019-07-02
10296701	Retiming with fixed power-up states	Mahesh A. Iyer, Vasudeva M. Kamath	2019-05-21
10255404	Retiming with programmable power-up states	Mahesh A. Iyer, Vasudeva M. Kamath	2019-04-09
10162918	Integrated circuit retiming with selective modeling of flip-flop secondary signals	Mahesh A. Iyer, Vasudeva M. Kamath	2018-12-25
9189583	Look-up based buffer tree synthesis	Sanjay Dhar, Kok Kiong Lee, Sanjay V. Kumar, Prashant Saxena	2015-11-17	$4,921,000
8621408	Progressive circuit evaluation for circuit optimization	Mahesh A. Iyer, Sudipto Kundu	2013-12-31	$10,449,000
8578321	Delta-slack propagation for circuit optimization	Mahesh A. Iyer	2013-11-05	$6,518,000
8527927	Zone-based area recovery in electronic design automation	Mahesh A. Iyer	2013-09-03	$3,459,000
8418116	Zone-based optimization framework for performing timing and design rule optimization	Mahesh A. Iyer, Amir H. Mottaez	2013-04-09	$4,983,000
8266570	Density-based area recovery in electronic design automation	Mahesh A. Iyer	2012-09-11	$2,907,000
6539536	Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics	Harbinder Singh, Denis Martin, Srinivas Ajjarapu	2003-03-25	$32,777,000
6106568	Hierarchical scan architecture for design for test applications	James Beausang, Chris Ellingham, Markus F. Robinson	2000-08-22	$33,109,000
6067650	Method and apparatus for performing partial unscan and near full scan within design for test applications	James Beausang, Kenneth D. Wagner	2000-05-23	$38,837,000
6058252	System and method for generating effective layout constraints for a circuit design or the like	Mark D. Noll, Kenneth E. Scott	2000-05-02	$19,031,000
5949692	Hierarchical scan architecture for design for test applications	James Beausang, Chris Ellingham, Markus F. Robinson	1999-09-07	$27,713,000
5911493	Illuminated umbrella	Leslie Ronald Wittenberg	1999-06-15
5903466	Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design	James Beausang, Chris Ellingham	1999-05-11	$15,026,000
5831868	Test ready compiler for design for test synthesis	James Beausang	1998-11-03	$40,458,000
5703789	Test ready compiler for design for test synthesis	James Beausang	1997-12-30	$28,047,000
5696771	Method and apparatus for performing partial unscan and near full scan within design for test applications	James Beausang, Kenneth D. Wagner	1997-12-09	$16,759,000

Robert Walker — 21 Patents

Issued Patents All Time

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