Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10936772 | Methods for incremental circuit physical synthesis | Mahesh A. Iyer, Robert Walker | 2021-03-02 |
| 10922461 | Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks | Mahesh A. Iyer | 2021-02-16 |
| 10489535 | Method and apparatus for reducing constraints during rewind structural verification of retimed circuits | Mahesh A. Iyer | 2019-11-26 |
| 10296701 | Retiming with fixed power-up states | Mahesh A. Iyer, Robert Walker | 2019-05-21 |
| 10255404 | Retiming with programmable power-up states | Mahesh A. Iyer, Robert Walker | 2019-04-09 |
| 10162918 | Integrated circuit retiming with selective modeling of flip-flop secondary signals | Mahesh A. Iyer, Robert Walker | 2018-12-25 |
| 10157247 | Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks | Mahesh A. Iyer | 2018-12-18 |