RC

Raghu Chalasani

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
MG Mentor Graphics: 1 patents #345 of 698Top 50%
Meta: 1 patents #4,098 of 6,845Top 60%
📍 San Jose, CA: #8,424 of 32,062 inventorsTop 30%
🗺 California: #82,707 of 386,348 inventorsTop 25%
Overall (All Time): #714,250 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
10922548 Systems and methods for automated video classification Lei Huang, Jianyu Wang, Guangshuo Liu, Renbin Peng, Ziheng Wang 2021-02-16
8671378 Method and system for distributing clock signals on non manhattan semiconductor integrated circuits Steven Teig, Akira Fujimura 2014-03-11
8533636 Tolerable flare difference determination Sergiy Komirenko, Nicolas B. Cobb 2013-09-10
8438525 Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits Steven Teig, Akira Fujimura 2013-05-07
7730441 Method and system for distributing clock signals on non manhattan semiconductor integrated circuit using parameterized rotation Steven Teig, Akira Fujimura 2010-06-01
7644384 Method and system for distributing clock signals on non-Manhattan semiconductor integrated circuits Steven Teig, Akira Fujimura 2010-01-05
7117470 Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits Steven Teig, Akira Fujimura 2006-10-03